UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-15 of 15 Help

Filters            
Selected(0)Clear Items/Page:    Sort:
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:23/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
Design and implementation of ultralow-power ZigBee/WPAN receiver Book
2015
Authors:  Lin Z.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
An open-loop multiphase local-oscillator generation technique Book
2016
Authors:  Un K.-F.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
A 0.4 v 6.4 μw 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °c for Wearable and Sensing Applications Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Lei K.-M.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:15/0  |  Submit date:2019/02/11
bootstrap  bulk-driven amplifier  CMOS  relaxation oscillator (RxO)  ultra-low-voltage (ULV)  wearable devices  
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
delay compensation  feedback loop  implantable medical devices  real time  voltage doubler  wireless power transfer  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
Novel second-order switched-capacitor interpolator Journal article
Electronics Letters, 1992,Volume: 28,Issue: 4,Page: 348-350
Authors:  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Circuit design  Digital filters  Signal processing  Switched-capacitor networks  
Optimum multistage multirate switched capacitor architectures for highly selective interface filtering Journal article
Electronics Letters, 1992,Volume: 28,Issue: 1,Page: 72-75
Authors:  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Analogue-digital conversion  Filtering  Switched capacitor filters  
An Optimum CMOS Switched-Capacitor Antialiasing Decimating Filter Journal article
IEEE Journal of Solid-State Circuits, 1993,Volume: 28,Issue: 9,Page: 962-970
Authors:  Franca J.E.;  Martins R.P.;  Maloberti F.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  U Seng-Pan;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
A novel algorithm for automated optimum design of IIR SC decimators Journal article
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002,Volume: 49,Issue: 4,Page: 293-296
Authors:  Ngai C.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Automated optimum design  Infinite-impulse response (IIR) switched-capacitor (SC) decimator  Linear/nonlinear programming  
Low-complexity, full-resolution, mirror-switching digital predistortion scheme for polar-modulated power amplifiers Journal article
Electronics Letters, 2012,Volume: 48,Issue: 24,Page: 1551-1553
Authors:  Yu W.-H.;  Cheng W.-F.;  Li Y.;  Cheang C.-F.;  Mak P.-I.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Micro-NMR on CMOS for biomolecular sensing Book
2017
Authors:  Lei K.-M.;  Sun M.;  Mak P.-I.;  Martins R.P.;  Ham D.
Favorite  |  View/Download:4/0  |  Submit date:2019/02/11
A dual-output SC converter with dynamic power allocation for multicore application processors Conference paper
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Authors:  Jiang J.;  Lu Y.;  Liu X.;  Ki W.-H.;  Mok P.K.T.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
background calibration  current integrating sampler  Time-interleaved ADC  timing skew