UM
(Note: the search results are based on claimed items)

Browse/Search Results:  1-20 of 72 Help

Filters            
Selected(0)Clear Items/Page:    Sort:
A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18 um CMOS Journal article
澳門機電工程專業協會(APEMEM)會刊, 2009
Authors:  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/28
Index Terms-pipelined Adc  Low-voltage  Current-mode Comparator  
1.2-V, 10-bit, 60– 360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 mm CMOS with minimised supply headroom Journal article
IET Circuits, Devices & Systems, 2010,Volume: 4,Issue: 1,Page: 1-13
Authors:  S.-W. Sin;  Seng-Pan U;  R.P. Martins
Favorite  |  View/Download:5/0  |  Submit date:2019/02/27
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:23/0  |  Submit date:2019/02/13
Bandwidth mismatches  split-digital to analog converter (DAC)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  time-interleaved (TI)  variance based  window detector (WD)  
A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator with 14.2-nJ Startup Energy and 31.8-μW Steady-State Power Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 9,Page: 2624-2635
Authors:  Lei K.-M.;  Mak P.-I.;  Law M.-K.;  Martins R.P.
Favorite  |  View/Download:18/0  |  Submit date:2019/02/11
Bluetooth Low-energy (Ble)  Chirping  Cmos  Crystal Oscillator (Xo)  Duty-cycling  Energy Harvesting (Eh)  Fast Startup  Internet-of-things (Iot)  Ultralow Power (Ulp)  Ultralow Voltage (Ulv)  
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite  |  View/Download:11/0  |  Submit date:2019/02/11
reference interference  SAR ADC  time-interleaved scheme  two-step SAR conversion  
IIR Switched-Capacitor Decimator Building Blocks with Optimum Implementation Journal article
IEEE Transactions on Circuits and Systems, 1990,Volume: 37,Issue: 1,Page: 81-90
Authors:  Franca J.A.E.;  Martins R.P.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Novel second-order switched-capacitor interpolator Journal article
Electronics Letters, 1992,Volume: 28,Issue: 4,Page: 348-350
Authors:  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:6/0  |  Submit date:2019/02/11
Circuit design  Digital filters  Signal processing  Switched-capacitor networks  
Optimum multistage multirate switched capacitor architectures for highly selective interface filtering Journal article
Electronics Letters, 1992,Volume: 28,Issue: 1,Page: 72-75
Authors:  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Analogue-digital conversion  Filtering  Switched capacitor filters  
An Optimum CMOS Switched-Capacitor Antialiasing Decimating Filter Journal article
IEEE Journal of Solid-State Circuits, 1993,Volume: 28,Issue: 9,Page: 962-970
Authors:  Franca J.E.;  Martins R.P.;  Maloberti F.
Favorite  |  View/Download:5/0  |  Submit date:2019/02/11
Switched-capacitor interpolators without the input sample-and-hold filtering effect Journal article
Electronics Letters, 1996,Volume: 32,Issue: 10,Page: 879-881
Authors:  Seng Pan U.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:10/0  |  Submit date:2019/02/11
Digital Filters  Signal Processing  Switched Capacitor Filters  
Impulse sampled FIR interpolation with SC active-delayed block polyphase structures Journal article
Electronics Letters, 1998,Volume: 34,Issue: 5,Page: 443-444
Authors:  U S.-P.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
High performance multirate SC circuits with predictive correlated double sampling technique Journal article
Proceedings - IEEE International Symposium on Circuits and Systems, 1999,Volume: 2
Authors:  U Seng-Pan;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:13/0  |  Submit date:2019/02/11
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity Journal article
Proceedings - IEEE International Symposium on Circuits and Systems, 1999,Volume: 2
Authors:  U Seng-Pan;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:7/0  |  Submit date:2019/02/11
Offset- and gain-compensated and mismatch-free SC delay circuit with flexible implementation Journal article
Electronics Letters, 1999,Volume: 35,Issue: 3,Page: 188-189
Authors:  Seng-Pan U.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:14/0  |  Submit date:2019/02/11
Improved switched-capacitor interpolators with reduced sample-and-hold effects Journal article
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000,Volume: 47,Issue: 8,Page: 665-684
Authors:  Seng-Pan U.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:8/0  |  Submit date:2019/02/11
A novel algorithm for automated optimum design of IIR SC decimators Journal article
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2002,Volume: 49,Issue: 4,Page: 293-296
Authors:  Ngai C.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:3/0  |  Submit date:2019/02/11
Automated optimum design  Infinite-impulse response (IIR) switched-capacitor (SC) decimator  Linear/nonlinear programming  
Two-step channel selection technique by programmable digital-double quadrature sampling for complex low-IF receivers Journal article
Electronics Letters, 2003,Volume: 39,Issue: 11,Page: 825-827
Authors:  Mak P.-I.;  Seng-Pan U;  Martins R.P.
Favorite  |  View/Download:15/0  |  Submit date:2019/02/11
Channel Allocation  Digital Phase Locked Loops  Phase Noise  Frequency Synthesizers  
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2004,Volume: 39,Issue: 1,Page: 87-99
Authors:  U S.-P.;  Martins R.P.;  Franca J.E.
Favorite  |  View/Download:17/0  |  Submit date:2019/02/11
Autozeroing  Bandpass  Cmos Analog Integrated Circuits  Direct-digital Synthesis  Filters  Frequency-translated Filtering  Interpolation  Multirate Signal Processing  Sampled Data Circuits  Signal Sampling/reconstruction  Switched-capacitor Filters  
Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects Journal article
IEEE Transactions on Instrumentation and Measurement, 2004,Volume: 53,Issue: 4,Page: 1279-1288
Authors:  U S.-P.;  Sin S.-W.;  Martins R.P.
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Spurious suppressed microstrip bandpass filter with two transmission zeros Journal article
Microwave and Optical Technology Letters, 2006,Volume: 48,Issue: 10,Page: 1979-1981
Authors:  Wai‐Wa Choi;  Kam‐Weng Tam;  R. P. Martins
Favorite  |  View/Download:9/0  |  Submit date:2019/02/11
Capacitive Stub  Spurious Suppression  Stepped Impedance  Transmission Zeros  Transversal Filter