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Sampling front-end for Analog to Digital Converter Patent
专利类型: 发明专利, 专利号: US20140368363A1, 申请日期: 2013-06-12, 公开日期: 2014-12-18
Authors:  Yan ZHU;  Chi Hang CHAN;  Sai Weng SIN;  Seng Pan U;  Rui Paulo da Silva MARTINS
Favorite | View/Download:2/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/06/04
N-bits successive approximation register analog-to-digital converting circuit Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01, 公开日期: 2013
Authors:  Yan Zhu;  Chi Hang Chan;  U Fat Chio;  Sai Weng Sin;;  Seng Pan U;  Rui Paulo Da Silva Martins;  Franco Maloberti
Favorite | View/Download:4/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/06/04
類比至數位轉換器電路 Patent
专利类型: 发明专利, 专利号: TW201242261A, 申请日期: 2011-03-08, 公开日期: 2012-10-16
Authors:  冼世荣;  丁立;  诸嫣;  魏和功;  陈知行;  赵汝法;  余成斌 U;  马许愿;  马洛贝尔蒂佛朗哥
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Comparator and calibration thereof Patent
专利类型: 发明专利, 专利号: US20140132307A1, 申请日期: 2012-11-13, 公开日期: 2014-05-15
Authors:  Chi Hang CHAN;  Yan ZHU;  U Fat CHIO;  Sai Weng SIN;  Seng Pan U;  Rui Paulo da SILVA MARTINS
Favorite | View/Download:2/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/06/03
類比至數位轉換器電路 Patent
专利类型: 发明专利, 专利号: TWI446723B, 申请日期: 2011-03-08, 公开日期: 2014-07-21
Authors:  冼世榮;  丁立;  诸嫣;  魏和功;  陈知行;  赵汝法;  余成斌 U;  马 许愿;  马洛贝尔蒂 佛朗哥
Favorite | View/Download:3/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2020/06/03
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: TW201242261A, 申请日期: 2011-03-08, 公开日期: 2012-10-16
Authors:  Xian SR(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chen ZX(陈知行);  Zhao RF(赵汝法);  余成斌 U;  Ma XY(马许愿);  马洛贝尔蒂 佛朗哥
Favorite | View/Download:12/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/04/18
N-Bits Successive Approximation Register Analog-to-Digital Converting System Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01, 公开日期: 2013
Authors:  Yan Zhu;  Chi Hang Chan;  U Fat Chio;  Sai Weng Sin;  Seng Pan U;  Rui Paulo Da Silva Martins;  Franco Maloberti
Favorite | View/Download:16/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Analog to Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: TWI446723B, 申请日期: 2011-03-08,
Authors:  Sin,S-W(冼世荣);  Ding L(丁立);  Zhu Y(诸嫣);  Wei HG(魏和功);  Chan CH(陈知行);  Chio UF(赵汝法);  U SP(余成斌);  Martins,R(马许愿);  Franco,M
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Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption Patent
专利类型: 发明专利, 专利号: US8427355B2, 申请日期: 2011-09-14,
Authors:  Sai-Weng Sin;  Li Ding;  Yan Zhu;  He-Gong Wei;  Chi-Hang Chan;  U-Fat Chio;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:11/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Sampling front-end for analog to digital converter Patent
专利类型: 发明专利, 专利号: US8947283B2, 申请日期: 2013-06-12, 公开日期: 2015-02-03
Authors:  Yan Zhu;  Chi-Hang Chan;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite | View/Download:16/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US8659461B1, 申请日期: 2012-11-13, 公开日期: 2014-02-25
Authors:  Yan Zhu;  Chi Hang Chan;  Sai Weng Sin;  Seng Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:14/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/30
Comparator and Calibration Thereof Patent
专利类型: 发明专利, 专利号: US8829942B2, 申请日期: 2012-11-13, 公开日期: 2014-09-09
Authors:  Chi-Hang CHAN;  Yan Zhu;  U-Fat CHIO;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins
Favorite | View/Download:12/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/06
N-Bits Successive Approximation Register Analog-to-Digital Converter Circuit Patent
专利类型: 发明专利, 专利号: US8344931B2, 申请日期: 2011-06-01,
Authors:  Yan Zhu;  Chi-Hang CHAN;  U-Fat CHIO;  Sai-Weng Sin;  Seng-Pan U;  Rui Paulo da Silva Martins;  Franco Maloberti
Favorite | View/Download:6/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/03/06
N-bits successive approximation register analog-to-digital converting circuit Patent
专利类型: 发明专利, 专利号: US20120306679A1, 申请日期: 2011-06-01,
Authors:  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Sai-Weng SIN;  Seng-Pan U;  Rui Paulo Da Silva MARTINS;  Franco MALOBERTI
Favorite | View/Download:12/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/26
Analog to digital converter circuit Patent
专利类型: 发明专利, 专利号: US20120229313A1, 申请日期: 2011-09-14, 公开日期: 2012-09-13
Authors:  Sai-Weng SIN;  He-Gong WEI;  Franco MALOBERTI;  Li DING;  Yan ZHU;  Chi-Hang CHAN;  U-Fat CHIO;  Seng-Pan U;  Rui Paulo da Silva MARTINS
Favorite | View/Download:11/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/26
Parasitic calibration by two-step ratio approaching techinque for split capacitor array SAR ADCs Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Wong S.-S.;  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:17/0 | TC[WOS]:5 TC[Scopus]:0 | Submit date:2019/02/11
Analog-to-digital Converter (Adc)  Offset Calibration  Parasitic Calibration  Split Capacitor Array  Sucessive Approximation Register (Sar)  
A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator Conference paper
2009 International SoC Design Conference, ISOCC 2009, Busan, South Korea, 22-24 Nov. 2009
Authors:  Chan C.-H.;  Zhu Y.;  Chio U.-F.;  Sin S.-W.;  U S.P.;  Martins R.P.
Favorite | View/Download:13/0 | TC[WOS]:10 TC[Scopus]:0 | Submit date:2019/02/11
Dynamic Comparator  Offset Calibration  
Comparator-based successive folding ADC Conference paper
1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, Shanghai, PEOPLES R CHINA, NOV 19-21, 2009
Authors:  Chio U.-F.;  Choi H.-L.;  Chan C.-H.;  Wong S.-S.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:8/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs Conference paper
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 30 May-2 June 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite | View/Download:13/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump Conference paper
Midwest Symposium on Circuits and Systems, Seattle, WA, AUG 01-04, 2010
Authors:  Zhu Y.;  Chan C.-H.;  Chio U.-F.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | View/Download:13/0 | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11