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A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing
Guo, Mingqiang1; Sin, Sai Weng1,2; Qi, Liang3; Xiao, Gangjun4; Martins, Rui P.1,5
2022
Conference Name2022 IEEE Custom Integrated Circuits Conference (CICC)
Source PublicationProceedings of the Custom Integrated Circuits Conference
Volume2022-April
Conference Date24-27 April 2022
Conference PlaceNewport Beach, CA, USA
Abstract

A SAR ADC comprises only a T/H, a comparator, SAR logics, and a capacitive DAC, thus exhibiting a power-efficient topology with low complexity, low power consumption, and friendly process technology scaling down. Consequently, it has a wide utilization in high-speed applications (like in time-interleaved SARs). Previous works improved the 1b/cycle topology to speed up SAR ADC conversions, leading to multi-bit/cycle [1] and N-bits N-comparators [2] structures. Compared with the above architectures, the conventional 1b/cycle topology still has apparent advantages related to low complexity, less parasitic, and less offset problems. Therefore, currently, the 1b/cycle is still the first choice for the majority of high-speed TI SAR ADCs [3]. The popularization of the high-speed SAR ADC with redundant bit structures can lead to a very short settling time required for the DACs [4]. However, the speed of the SAR is still a bottleneck, especially limited by the digital SAR logic [2].

DOI10.1109/CICC53496.2022.9772843
URLView the original
Indexed ByCPCI-S
Language英語English
Scopus ID2-s2.0-85130756453
Fulltext Access
Citation statistics
Document TypeConference paper
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorSin, Sai Weng
Affiliation1.University of Macau, Macao
2.Zhuhai UM Science, Technology Research Institute, Zhuhai, China
3.Shanghai Jiao Tong University, Shanghai, China
4.Amicro Semiconductor Co., Ltd, Zhuhai, China
5.University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Guo, Mingqiang,Sin, Sai Weng,Qi, Liang,et al. A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing[C],2022.
APA Guo, Mingqiang,Sin, Sai Weng,Qi, Liang,Xiao, Gangjun,&Martins, Rui P..(2022).A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing.Proceedings of the Custom Integrated Circuits Conference,2022-April.
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