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A 21.8–41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and –250.3dB FoM
Chen, Wen1; Shu, Yiyang1; Qan, Huizhen Jenny1; Yin, Jun2; Mak, Pui-In2; Gao, Xiang3; Luo, Xun1
2022-06
Conference NameIEEE Radio-Frequency Integrated Circuits Symposium (RFIC)
Conference Date2022-06
Conference PlaceDenver, CO
CountryUSA
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Corresponding AuthorChen, Wen; Luo, Xun
Affiliation1.University of Electronic Science and Technology of China
2.University of Macau, Institite of Microelectronics
3.Zhejiang University
Recommended Citation
GB/T 7714
Chen, Wen,Shu, Yiyang,Qan, Huizhen Jenny,et al. A 21.8–41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and –250.3dB FoM[C],2022.
APA Chen, Wen,Shu, Yiyang,Qan, Huizhen Jenny,Yin, Jun,Mak, Pui-In,Gao, Xiang,&Luo, Xun.(2022).A 21.8–41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and –250.3dB FoM..
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