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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Mao, Jiaji; Guo, Mingqiang; Sin, Sai-Weng; Martins, Rui Paulo
2018-10
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume65Issue:10Pages:1380-1384
Abstract

Pipeline analog-to-digital converters (ADCs), which dominated high-speed and high-resolution applications, suffered from weak improvement in power efficiency. To address such a problem, this brief presents a 14-bit split-pipeline opamp-sharing ADC, with background calibration that optimizes duty-cycle ratio and amplifier power consumption in the shared opamp. Based on the interstage gain (that includes settling) error estimated by the split ADC calibration engine, the clock duty-cycle ratio and the bias current are adjusted to achieve better dynamic settling and resolution trade-offs. Operating at 100 MS/s with a 9-MHz input signal, the ADC achieves 46.5 dB of signal-to-noise-and-distortion ratio (SNDR) and 59.6 dB of spurious-free dynamic range (SFDR) before calibration, and after calibration, it improves to 71.7 dB of SNDR and 84.4 dB of SFDR, respectively. The ADC maintains an SNDR over 68.5 dB within the full Nyquist bandwidth consuming 32 mW of power, which yields a Walden figure-of-merit (FoM) of 147.2 fJ/conversion-step and a Schreier FoM of 160.4 dB.

KeywordAnalog-to-digital Conversion Digital Background Calibration Pipelined Adc Split Adc Opamp-sharing Technique
DOI10.1109/TCSII.2018.2851944
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000446155600020
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
The Source to ArticleWOS
Scopus ID2-s2.0-85049327736
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Citation statistics
Cited Times [WOS]:7   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Faculty of Science and Technology
Recommended Citation
GB/T 7714
Mao, Jiaji,Guo, Mingqiang,Sin, Sai-Weng,et al. A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current[J]. IEEE Transactions on Circuits and Systems II: Express Briefs,2018,65(10):1380-1384.
APA Mao, Jiaji,Guo, Mingqiang,Sin, Sai-Weng,&Martins, Rui Paulo.(2018).A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current.IEEE Transactions on Circuits and Systems II: Express Briefs,65(10),1380-1384.
MLA Mao, Jiaji,et al."A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current".IEEE Transactions on Circuits and Systems II: Express Briefs 65.10(2018):1380-1384.
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