UM  > INSTITUTE OF MICROELECTRONICS
Affiliated with RCfalse
Status已發表Published
A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input
Zhang,Minglei1; Zhu,Yan1; Chan,Chi Hang1; Martins,Rui P.1,2
2020-04-13
Conference Name2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2020-February
Pages252-254
Conference Date16-20 Feb. 2020
Conference PlaceSan Francisco, CA, USA
Abstract

The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR ADCs with a large interleaving factor suffer from a large input capacitance [1] and often have a limited BW, or otherwise they necessitate a power-hungry broadband input buffer [2]. Flash ADCs [3] not only face the same challenge from the large input parasitics but also limited resolutions resulting from offset. Recently, time-domain ADCs [4], [5] have shown promising speeds resulting from a small input capacitance due to their inherent voltage-to-time converter (VTC) as a sub-channel wideband buffer, but also show limited resolution (6b) due to the mismatches between the time steps. When targeting a higher resolution [6], calibration is necessary to unify the time quantization steps and often requires a known input condition with a large lookup table, thus introducing complexity. In this work, a 10 GS/s ADC is achieved by just aggregating four 8b two-stage time-domain ADCs running at 2.5GS/s. The gain between the stages is inherently defined by a 16x time interpolator in the second stage, which not only saves power but also allows the time quantization steps to be free from calibration. The presented time-domain ADC achieves >37.5dB SNDR at an 18GHz input due to its small input capacitance and buffer-like VTC, and also obtains a metastability error rate <10 through a timing-extended residue transfer scheme. Moreover, the time quantization in the two-stage ADC also shows PVT robustness benefits from the interpolation-based gain.

DOI10.1109/ISSCC19947.2020.9062986
URLView the original
Language英語English
Scopus ID2-s2.0-85083826324
Fulltext Access
Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.University of Macau,Macao
2.University of Lisboa,Lisbon,Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zhang,Minglei,Zhu,Yan,Chan,Chi Hang,et al. A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input[C],2020:252-254.
APA Zhang,Minglei,Zhu,Yan,Chan,Chi Hang,&Martins,Rui P..(2020).A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input.Digest of Technical Papers - IEEE International Solid-State Circuits Conference,2020-February,252-254.
Files in This Item:
There are no files associated with this item.
Related Services
Recommend this item
Bookmark
Usage statistics
Export to Endnote
Google Scholar
Similar articles in Google Scholar
[Zhang,Minglei]'s Articles
[Zhu,Yan]'s Articles
[Chan,Chi Hang]'s Articles
Baidu academic
Similar articles in Baidu academic
[Zhang,Minglei]'s Articles
[Zhu,Yan]'s Articles
[Chan,Chi Hang]'s Articles
Bing Scholar
Similar articles in Bing Scholar
[Zhang,Minglei]'s Articles
[Zhu,Yan]'s Articles
[Chan,Chi Hang]'s Articles
Terms of Use
No data!
Social Bookmark/Share
All comments (0)
No comment.
 

Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.