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A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis | |
Chen,Yong1,2![]() | |
2019-10-01 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers
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ISSN | 1549-8328 |
Volume | 66Issue:10Pages:3991-4004 |
Abstract | This paper proposes an ultra-compact 4 to 10-Gb/s 5-Tap current-mode transmitter to realize the sub 1-UI fractional de-emphasis (DE) using a hybrid delay line, which is alternatively controlled by the voltage bias and clock. It exhibits the scalability between the clocked 0.5-UI and 1-UI DEs and data rate. The sub-1-UI DE provides wide tunability of the data amplitude and delay to compensate different channel losses between the 1{st} and 2{nd} Nyquist frequencies while effectively compensating the high-frequency portion of the pseudo-random binary sequence (PRBS) spectrum for data jitter improvement. Additional techniques are a two-step current-summing scheme, namely, two-step DE in the data path, and active inductors in both the data and clock paths to enhance the internal bandwidth without the need for passive inductors. In addition, we present an analytical model for predicting data-dependent jitter (DDJ) based on a generic system's step response, derive the exact closed-form DDJ expression of DE, and verify its validity by mean of circuit simulation. Prototyped in 65-nm CMOS technology, it achieves a figure-of-merit of 4.6 mW/Gb/s and an output jitter of 10.8 ps at 10 Gb/s under a PRBS 2{31}-1 pattern. The data eyes measure 0.62-UI-horizontal and 19.5%-vertical openings after-20-dB channel loss. The die area is 0.0071 mm. |
Keyword | Active Inductor (Ai) Bandwidth (Bw) Extension Cmos Current Reuse Current-mode Logic (Cml) Current-mode Transmitter Data-dependent Jitter (Ddj) Figure-of-merit (Fom) Flip-flop (Ff) Fractional De-emphasis (De) Hybrid Delay Line Latch Pulse-width-modulated (Pwm) Unit Interval (Ui) |
DOI | 10.1109/TCSI.2019.2919623 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000489730200031 |
Scopus ID | 2-s2.0-85072983525 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Chen,Yong |
Affiliation | 1.State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macao 2.Department of ECE,Faculty of Science and Technology,University of Macau,999078,Macao 3.Department of Electrical and Electronic Engineering,Nanyang Technological University,Singapore,Singapore 4.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1049-001,Portugal |
First Author Affilication | University of Macau; Faculty of Science and Technology |
Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Chen,Yong,Mak,Pui In,Yang,Zunsong,et al. A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2019,66(10):3991-4004. |
APA | Chen,Yong,Mak,Pui In,Yang,Zunsong,Boon,Chirn Chye,&Martins,Rui P..(2019).A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.IEEE Transactions on Circuits and Systems I: Regular Papers,66(10),3991-4004. |
MLA | Chen,Yong,et al."A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis".IEEE Transactions on Circuits and Systems I: Regular Papers 66.10(2019):3991-4004. |
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