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A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration
Huang,Mo1,2; Chen,Dihu1,2; Guo,Jianping1,2; Ye,Hui3; Xu,Ken3; Liang,Xiaofeng1,2; Lu,Yan4
2015-07-01
Source PublicationIEEE Transactions on Circuits and Systems I: Regular Papers
ISSN1549-8328
Volume62Issue:7Pages:1716-1725
AbstractA delta-sigma (ΔΣ)phase locked loop (PLL) transmitter with an efficient modulation bandwidth calibration technique is proposed in this paper. With the proposed technique, the digital-analog mismatch between digital pre-emphasis filter and PLL is calibrated. The loop filter RC variation is tracked in the first place, and then the variation of the loop gain is calibrated by sensing the magnitude differences of the modulator between DC and ten times of the loop bandwidth. The proposed transmitter has been implemented in 0.18-μm CMOS technology for GSM/GPRS application. Measurement results show that the maximum RMS phase error of the proposed transmitter is 0.8° . In addition, the measured calibration accuracies for RC and loop gain variations are 0.5% and 0.8%, respectively. By reusing the PLL locking time, 18-μs calibration time is achieved. Moreover, most parts of the calibration circuitries can be shared with the receiver chain, reducing the circuit complexity overhead.
KeywordDelta-sigma phase locked loop (PLL) modulation bandwidth calibration transmitters
DOI10.1109/TCSI.2015.2441965
URLView the original
Language英語English
Scopus ID2-s2.0-85027951204
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Cited Times [WOS]:9   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionUniversity of Macau
Affiliation1.School of Physics and Engineering,Sun Yat-sen University,Guangzhou,510275,China
2.SYSU-CMU Shunde International Joint Research Institute,Foshan,528300,China
3.School of Electronics and Information Engineering,South China University of Technology,Guangzhou,China
4.State Key Laboratory of Analog and Mixed-Signal VLSI of University of Macau,Macao,Macao
Recommended Citation
GB/T 7714
Huang,Mo,Chen,Dihu,Guo,Jianping,et al. A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration[J]. IEEE Transactions on Circuits and Systems I: Regular Papers,2015,62(7):1716-1725.
APA Huang,Mo,Chen,Dihu,Guo,Jianping,Ye,Hui,Xu,Ken,Liang,Xiaofeng,&Lu,Yan.(2015).A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration.IEEE Transactions on Circuits and Systems I: Regular Papers,62(7),1716-1725.
MLA Huang,Mo,et al."A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration".IEEE Transactions on Circuits and Systems I: Regular Papers 62.7(2015):1716-1725.
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