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Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
Sun, Jie1; Zhang, Minglei2; Qiu, Lei3; Wu, Jianhui4; Liu, Weiqiang1
2020-04-01
Source PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN1063-8210
Volume28Issue:4Pages:1074-1078
Abstract

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.

KeywordBackground Calibration Bit Weight Dither Injection Pipelined Sar Adc Residue Increment
DOI10.1109/TVLSI.2019.2961149
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaComputer Science ; Engineering
WOS SubjectComputer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS IDWOS:000522421700019
Scopus ID2-s2.0-85082508317
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Cited Times [WOS]:7   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
Corresponding AuthorSun, Jie; Zhang, Minglei
Affiliation1.School of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, China
2.State Key Laboratory of Analog and Mixed Signal, University of Macau, Zhuhai, 999078, China
3.School of Electronic and Information Engineering, Tongji University, Shanghai, China
4.School of Electronics Science and Engineering, Southeast University, Nanjing, China
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Sun, Jie,Zhang, Minglei,Qiu, Lei,et al. Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2020,28(4):1074-1078.
APA Sun, Jie,Zhang, Minglei,Qiu, Lei,Wu, Jianhui,&Liu, Weiqiang.(2020).Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators.IEEE Transactions on Very Large Scale Integration (VLSI) Systems,28(4),1074-1078.
MLA Sun, Jie,et al."Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators".IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28.4(2020):1074-1078.
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