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A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations
Zhang, Yanbo1,2; Zhang, Jin1,2; Liu, Shubin1; Ding, Ruixue1; Zhu, Yan2; Chan, Chi Hang2; Martins, Rui P.1
2022-03-01
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume57Issue:3Pages:745-756
Abstract

This article presents a second-order successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) with optimized noise transfer function (NTF) zeros, background inter-stage gain, and offset calibrations. The NS, realized with an error-feedback (EF) structure, takes place in the second stage of the pipeline. A single amplifier, utilized for residue handover, realizes the EF and the optimized zeros. Copies of the EF capacitors allow their rotation role for residue saving, feedback, and sampling operations, thus omitting the extra phase for the EF operation. While further incorporating a coarse SAR ADC and partial interleaving techniques, the prototype can run at high speed with low power and strong in- band noise suppression. A split-over-time architecture with level-shift-based gain calibration is introduced to ensure the robustness of the ADC, whose hardware also facilitates the offset calibration. Besides, the split second-stage ADCs also share a single comparator, thus enabling a mismatch error insensitive split-ADC architecture with a fast convergence speed of 4000 cycles. Fabricated in 28 nm CMOS, the ADC prototype runs at a 260 MHz sampling rate and retains 20 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 79.1 dB under a small over-sampling ratio (OSR) of 6.5. It consumes 3.1 mW power at a 1 V supply and yields a Schreier figure-of-merit (FoMS) of 177.2 dB.

KeywordAnalog-to-digital Converter (Adc) Inter-stage Gain And Offset Calibrations Noise-shaping (Ns) Split Adc Successive Approximation Register (Sar)-assisted Pipeline
DOI10.1109/JSSC.2021.3137342
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:000761214100012
Scopus ID2-s2.0-85122589175
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Cited Times [WOS]:0   [WOS Record]     [Related Records in WOS]
Document TypeJournal article
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorChan, Chi Hang
Affiliation1.State Key Laboratory of Analog and Mixed Signal VLSI, Department of Electrical and Computer Engineering, Faculty of Science and Technology, Institute of Microelectronics, University of Macau, Macao, Macao
2.Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi'an, 710071, China
First Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Zhang, Yanbo,Zhang, Jin,Liu, Shubin,et al. A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations[J]. IEEE Journal of Solid-State Circuits,2022,57(3):745-756.
APA Zhang, Yanbo,Zhang, Jin,Liu, Shubin,Ding, Ruixue,Zhu, Yan,Chan, Chi Hang,&Martins, Rui P..(2022).A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations.IEEE Journal of Solid-State Circuits,57(3),745-756.
MLA Zhang, Yanbo,et al."A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations".IEEE Journal of Solid-State Circuits 57.3(2022):745-756.
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