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1. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS [224]
2. N-Bits Successive Approximation Register Analog-to-Digital Convert.. [209]
3. A dual-symmetrical-output switched-capacitor converter with dynami.. [176]
4. Accuracy-enhanced variance-based time-skew calibration using SAR a.. [157]
5. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With B.. [149]
6. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined R.. [140]
7. A sub-1V 78-nA bandgap reference with curvature compensation [140]
8. A reconfigurable bidirectional wireless power transceiver with max.. [132]
9. Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC with Partial .. [132]
10. A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesti.. [131]
11. Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with O.. [129]
12. A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC f.. [124]
13. A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Ba.. [122]
14. Sampling front-end for analog to digital converter [119]
15. A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around .. [114]
16. Analog to digital converter circuit [114]
17. 類比至數位轉換系統 [114]
18. A dual-output SC converter with dynamic power allocation for multi.. [113]
19. A digital LDO with transient enhancement and limit cycle oscillati.. [113]
20. A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with sing.. [111]
21. Delay generator [111]
22. N-Bits Successive Approximation Register Analog-to-Digital Convert.. [110]
23. Active-Passive Delta Sigma Modulator for High-Resolution and Low-P.. [109]
24. Design and experimental verification of a power effective Flash-SA.. [109]
25. A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Increm.. [109]
26. On-chip small capacitor mismatches measurement technique using bet.. [108]
27. N-bits successive approximation register analog-to-digital convert.. [108]
28. Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S pi.. [107]
29. A reconfigurable low-noise dynamic comparator with offset calibrat.. [107]
30. Analog to Digital Converter Circuit [106]
31. Self-Reconfiguration Property of a Mixed Signal Controller for Imp.. [105]
32. A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC [105]
33. 延迟产生器 [104]
34. Metastablility in SAR ADCs [103]
35. A FPGA-based power electronics controller for hybrid active power .. [103]
36. 類比至數位轉換器電路 [103]
37. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interl.. [102]
38. A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC [101]
39. DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireles.. [101]
40. 類比至數位轉換器電路 [101]
41. FPGA-based decoupled double synchronous reference frame PLL for ac.. [100]
42. Analog to digital converter circuit [100]
43. DC-OFFSET CANCELLED PROGRAMMABLE GAIN ARRAY FOR LOW-VOLTAGE WIRELE.. [99]
44. An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SA.. [97]
45. An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC [97]
46. Multi-merged-switched redundant capacitive DACs for 2b/cycle SAR A.. [97]
47. A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS.. [96]
48. ANALOG-TO-DIGITAL CONVERTING SYSTEM [96]
49. A power scalable 6-bit 1.2GS/s flash ADC with power on/off track-a.. [95]
50. Comparator and Calibration Thereof [95]
51. Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low .. [95]
52. A voltage-controlled capacitance offset calibration technique for .. [94]
53. Generalized Low-Voltage Circuit Techniques for Very High-Speed Tim.. [94]
54. A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrat.. [92]
55. An all-factor modulation bandwidth extension technique for delta-s.. [92]
56. A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 6.. [92]
57. Design of Very High-Frequency Multirate Switched-Capacitor Circuit.. [92]
58. A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset ca.. [91]
59. A review and design of the on-chip rectifiers for RF energy harves.. [91]
60. Design techniques for nanometer wideband power-efficient CMOS ADCs [91]
61. Noise shaping implementation in two-step/SAR ADC architectures bas.. [91]
62. Offset- and gain-compensated and mismatch-free SC delay circuit wi.. [91]
63. Cascade Analog to Digital Converting System [91]
64. A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC.. [90]
65. A Dual-Output Wireless Power Transfer System With Active Rectifier.. [89]
66. A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-inte.. [89]
67. A charge pump based timing-skew calibration for time-interleaved A.. [89]
68. Linearity analysis on a series-split capacitor array for high-spee.. [89]
69. A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS [88]
70. A time-efficient dither-injection scheme for pipelined SAR ADC [88]
71. Split-SAR ADCs: Improved linearity with power and speed optimizati.. [87]
72. A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolati.. [87]
73. A passive excess-loop-delay compensation technique for Gm-C based .. [87]
74. A power effective 5-bit 600 MS/s binary-search ADC with simplified.. [87]
75. An output-capacitor-free analog-assisted digital low-dropout regul.. [86]
76. A dual-VCO-based quantizer with highly improved linearity and enla.. [86]
77. A power-efficient capacitor structure for high-speed charge recycl.. [86]
78. Two-step channel selection technique by programmable digital-doubl.. [86]
79. Thermal and Reference Noise Analysis of Time-Interleaving SAR and .. [85]
80. A nonlinearity digital background calibration algorithm for 2.5bit.. [85]
81. Exact spectra analysis of sampled signals with jitter-induced nonu.. [85]
82. A rapid power-switchable track-and-hold amplifier in 90-nm CMOS [84]
83. A 5-bit 1.25-GS/s 4x-capacitive-folding flash ADC in 65-nm CMOS [84]
84. Analog to digital converter circuit [84]
85. An 8-b 400-ms/s 2-b-per-cycle sar adc with resistive dac [83]
86. A 6.78 MHz active voltage doubler with near-optimal on/off delay c.. [83]
87. Two-step channel selection for wireless receiver and transmitter f.. [82]
88. NTF zero compensation technique for passive sigma-delta modulator [80]
89. Clock-jitter sensitivity reduction in CT ΣΔ modulators using vol.. [80]
90. A Process- and temperature- insensitive current-controlled delay g.. [80]
91. High performance multirate SC circuits with predictive correlated .. [80]
92. A Digital PWM Controlled KY Step-Up Converter based on Passive Sig.. [79]
93. An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused .. [79]
94. A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit fla.. [79]
95. A novel very low-voltage SC-CMFB technique for fully-differential .. [79]
96. A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Rese.. [79]
97. Transceiver Architecture Selection–– Review, State-of-the-Art Su.. [79]
98. Capacitive Floating Level Shifter: Modeling and Design [78]
99. A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC st.. [78]
100. A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized numb.. [78]

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