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A 108-nW 0.8-mm 2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 11,Page: 1-10
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/07/22
Approximate Computing  Convolutional Neural Network (Cnn)  Feature Extraction  Keyword Spotting (Kws)  Quantization  Reconfigurable  Sparsity  Switched-capacitor Circuits  Voice Activity Detection (Vad)  
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 64-74
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
Compendious concurrent dual-band receiver based on multiport interferometric architecture Journal article
IEEE Transactions on Microwave Theory and Techniques, 2021,Page: 3388-3398
Authors:  Cheong, P.;  Wu, K.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/08/11
Bit-error-rate (Ber)  Channel Imbalance  Dualband  Interchannel Interference  In-phase And Quadrature (Iq) Imbalance  Multiport Receiver  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Microelectronics Journal, 2021,Volume: 113
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken;  Jing, Xixin;  Zhang, Bing;  Gui, Xiaoyan;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date：2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:14 TC[Scopus]:16 | Submit date：2021/03/04
Analog-to-digital Converter  Background Timing Skew Calibration  Current Integrating Sampler  Sar Adc  Time-interleaved Adc  Timing Skew  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zheng, Zihao;  Wei, Lai;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:12 TC[Scopus]:13 | Submit date：2021/03/04
Analog-to-digital Converter (Adc)  And Temperature (Pvt) Robustness  High-speed Adc  Metastability  Process  Supply Voltage  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)