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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
IEEE Open Journal of the Solid-State Circuits Society, 2021,Page: 129-139
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
Compendious Concurrent Dual-Band Receiver Based on Multiport Interferometric Architecture Journal article
IEEE Transactions on Microwave Theory and Techniques, 2021,Volume: 69,Issue: 7,Page: 3388-3398
Authors:  Pedro Cheong;  Wu, Ke
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/12/08
Bit-error-rate (Ber)  Channel Imbalance  Dual-band  In-phase And Quadrature (Iq) Imbalance  Interchannel Interference  Multiport Receiver  
Angular Domain Channel Estimation for mmWave Massive MIMO with One-Bit ADCs/DACs Journal article
IEEE Transactions on Wireless Communications, 2021,Volume: 20,Issue: 2,Page: 969-982
Authors:  Xu, Liangyuan;  Qian, Cheng;  Gao, Feifei;  Zhang, Wei;  Ma, Shaodan
Favorite |  | TC[WOS]:5 TC[Scopus]:8 | Submit date:2021/12/07
Angular Domain  Channel Estimation  Multi-user Massive Mimo  One-bit Analogto-digital Converter  One-bit Digital-to-analog Converter  Precoding  Uplink/downlink  
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Proceedings - International SoC Design Conference 2021, ISOCC 2021, Jeju Island, Korea, Republic of, 06-09 October 2021
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2022/05/13
Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 12,Page: 4174-4186
Authors:  Wang,Hanyu;  Sin,Sai Weng;  Lam,Chi Seng;  Maloberti,Franco;  Martins,Rui Paulo
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2021/03/04
Power Management  Switching-mode Power Converters  Boost Dc-dc Converters  Analog-to-digital Converters (Adcs)  Pipelined Adc  Ripple Calibration  
Systems for Concurrent Dual-Band Interferometric Transceiver Based on Multiport Architecture Patent
专利类型: 发明专利Invention,
Authors:  Pedro Cheong;  Wu, Ke
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A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite |  | TC[WOS]:8 TC[Scopus]:10 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch  
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,Volume: 28,Issue: 4,Page: 1074-1078
Authors:  Sun, Jie;  Zhang, Minglei;  Qiu, Lei;  Wu, Jianhui;  Liu, Weiqiang
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date:2021/10/28
Background Calibration  Bit Weight  Dither Injection  Pipelined Sar Adc  Residue Increment