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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1480-1491
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
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Amplifier linearity enhancement  Analog-to-digital converter (ADC)  Background offset calibration  Digital reconstruction filter  DWA  Energy and area efficient  Inherent gain error tolerant  Inter-stage gain error  Noise shaping (NS)  Oversampling  Partial interleaving  Pipelined successive approximation (SAR)  Quantization leakage error  
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1358-1371
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
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and zero net current (ZNC)  Bang-bang clock and data recovery (BBCDR)  charge pump (CP)  CMOS  four-level pulse-amplitude modulation (PAM)  frequency detector (FD)  half-rate  negative net current (NNC)  positive net current (PNC)  reference-less  
A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems Journal article
Analog Integrated Circuits and Signal Processing, 2022,Volume: 111,Issue: 1,Page: 35-43
Authors:  Pakkirisami Churchill, Kishore Kumar;  Ramiah, Harikrishnan;  Chong, Gabriel;  Ahmad, Mohd Yazed;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
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Charge Pump  Dc-to-dc Conversion  Dynamic Voltage Frequency Scaling (Dvfs)  Energy Harvesting  Ring-voltage ContRolled Oscillator (Ro)  
A 240 µW 17 bit ENOB ∆Σ modulator using 2nd-order noise-shaped integrating quantizer Journal article
IEICE Electronics Express, 2022,Volume: 19,Issue: 5
Authors:  Wang, Kunyu;  Xu, Wenjing;  Zhang, Chengbin;  Law, Man Kay;  Zhou, Li;  Chen, Ming;  Chen, Jie
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Analog-to-digital conversion  Noise enhancement circuit  Noise-shaping quantizer  ∆Σ modulator  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 745-756
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
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Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 3,Page: 1159-1170
Authors:  He, Jian;  Zhang, Yuguang;  Liu, Han;  Liao, Qiwen;  Zhang, Zhao;  Li, Miaofeng;  Jiang, Fan;  Shi, Jingbo;  Liu, Jian;  Wu, Nanjian;  Chen, Yong;  Chiang, Patrick Yin;  Yu, Ningmei;  Xiao, Xi;  Qi, Nan
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Artificial Transmission Line (t-Line)  Cmos  Distributed Driver  Extinction Ratio (Er)  Feed-forward Equalizer (Ffe)  High-swing  Mach-zehnder Modulator (Mzm)  Nrz  Optical Interconnects  Pam-4  Push-pull  Silicon-photonics  
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 767-780
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang;  Li, Guike;  Zhang, Zhao;  Liu, Jian;  Wu, Nanjian;  Liu, Liyuan;  Chen, Yong;  Xiao, Xi;  Qi, Nan
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Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 2,Page: 546-561
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
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Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022,Volume: 30,Issue: 2,Page: 238-242
Authors:  Yang, Zunsong;  Chen, Yong;  Yuan, Jia;  Mak, Pui In;  Martins, Rui P.
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Binary Frequency Shift Keying (Bfsk)  Frequency-locked Loop (Fll)  Integer-n  Phase Detector (Pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Push-pull  Reference (Ref) Spur  Sub-sampling (Ss)  Voltage-controlled Oscillator (Vco)  
A 1.7–3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4–4.8 dB NF Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 2,Page: 413-422
Authors:  Shao, Haijun;  Qi, Gengzhen;  Mak, Pui In;  Martins, Rui P.
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Bandpass Filtering  Gain  Impedance  Linearity  Noise Measurement  Passband  Radio Frequency  Transformers