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Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,Volume: 28,Issue: 4,Page: 1074-1078
Authors:  Sun, Jie;  Zhang, Minglei;  Qiu, Lei;  Wu, Jianhui;  Liu, Weiqiang
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date:2021/10/28
Background Calibration  Bit Weight  Dither Injection  Pipelined Sar Adc  Residue Increment  
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:  Rui Wang;  U-Fat Chio;  Sai-Weng Sin;  Seng-Pan U;  Zhihua Wang;  Rui Paulo Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:15 | Submit date:2019/02/11
Sar Adc  Pipelined  Digital Calibration  Op-amp Sharing  
A time-efficient dither-injection scheme for pipelined SAR ADC Conference paper
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, Macau, China, 6-7 Oct. 2011
Authors:  Wang R.;  Chio U.-F.;  Chan C.-H.;  Ding L.;  Sin S.-W.;  Seng-Pan U.;  Wang Z.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2019/02/11
Digital Calibration  Dither Injection  Pipelined  Sar Adc