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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1480-1491
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
锌铝空气电池模具 Patent
专利类型: 外观设计Appearance design, 专利号: CN202130419546.1, 申请日期: 2021-07-05,
Authors:  許冠南
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/25
Single-loop linear-exponential multi-bit incremental analog-to-digital converter Patent
专利号: US10644718B1, 申请日期: 2019-05-07, 公开日期: 2020-05-05
Authors:  Wang, Biao;  Sin, Sai-Weng;  Maloberti, Franco;  Martins, Rui Paulo da Silva
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/21
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC with Background Inter-Stage Offset Calibration Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, FEB 16-20, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2021/03/04
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Gain  Noise-shaping (Ns)  Offset Calibration  Pipelines  Registers  Successive Approximation Register (Sar)-assisted Pipeline  System-on-chip  Time Interleaving.  Transfer Functions  
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, JUN 18-22, 2018
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  MartinMartinss R.P.
Favorite |  | TC[WOS]:20 TC[Scopus]:7 | Submit date:2019/02/11
A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits (Invited Special Issue of VLSI), 2019,Page: 1161-1172
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Analog-to-digital Converter  Iadc  Incremental Adc  Sigma-delta  Linear  Exponential  Accumulation  Two-phase  Multi-bit  Mismatch Error  Dynamic Element Matching (Dem)  Data Weighting Average (Dwa)  High Linearity  Notch  
A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 4,Page: 1161-1172
Authors:  Wang, B.;  Sin,Sai Weng;  Seng-Pan,S. P.U.;  Maloberti,Franco;  Martins,Rui P.
Favorite |  | TC[WOS]:20 TC[Scopus]:22 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Data Weighting Average  Dynamic Element Matching (Dem)  High Linearity  Incremental Adc (iAdc)  Linear-exponential Accumulation  Mismatch Error  Multi-bit  Notch  Sigma Delta  Two Phase