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A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 64-74
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2020/12/04
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ct-dsm)  Preliminary Sampling And Quantization (Psq) Technique  Single Amplifier Biquad (Sab)  Successiveapproximation-register (Sar) Architecture-based Quantizer (Qtz)  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:17 TC[Scopus]:18 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
20.7 A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:12 | Submit date:2020/12/04
Excess-loop-delay compensation technique for CT Delta Sigma modulator with hybrid active-passive loop-filters Journal article
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013,Page: 35-46
Authors:  Cai, C.Y.;  Jiang, Y.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/24
CT Delta Sigma modulator  Hybrid active-passive loop-filter  Excess-loop-delay for hybrid active-passive loop-filter  Excess-loop-delay compensation techniques for hybrid active-passive loop-filter  
Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters Journal article
Analog Integrated Circuits and Signal Processing, 2013,Volume: 76,Issue: 1,Page: 35-46
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
Ct Δς Modulator  Excess-loop-delay Compensation Techniques For Hybrid Active-passive Loop-filter  Excess-loop-delay For Hybrid Active-passive Loop-filter  Hybrid Active-passive Loop-filter  
An ELD tracking compensation technique for active-RC CT ΣΔ modulators Conference paper
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, USA, AUG 05-08, 2012
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui. P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2019/02/11
A passive excess-loop-delay compensation technique for Gm-C based continuous-time ΣΔ modulators Conference paper
Midwest Symposium on Circuits and Systems, Yonsei Univ, Seoul, SOUTH KOREA, AUG 07-10, 2011
Authors:  Cai C.-Y.;  Jiang Y.;  Sin S.-W.;  U S.-P.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:7 | Submit date:2019/02/11