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A 240 µW 17 bit ENOB ∆Σ modulator using 2nd-order noise-shaped integrating quantizer Journal article
IEICE Electronics Express, 2022,Volume: 19,Issue: 5
Authors:  Wang, Kunyu;  Xu, Wenjing;  Zhang, Chengbin;  Law, Man Kay;  Zhou, Li;  Chen, Ming;  Chen, Jie
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/13
Analog-to-digital Conversion  Noise Enhancement Circuit  Noise-shaping Quantizer  ∆σ Modulator  
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
Expert vs. Influencer: Philosophy Presented under Conditions of Second-Order Observation Journal article
Human Affairs, 2021,Volume: 31,Issue: 4,Page: 470-478
Authors:  Moeller, Hans-Georg;  O/Neill, Rory;  Chiang, Hio Fai
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/09
Academic System, Peer Review, Social Media, Youtube, Second-order Observation, Niklas Luhmann  
Cascaded Form Sparse FIR Filter Design Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 5,Page: 1692-1703
Authors:  Chen, Wangqian;  Huang, Mo;  Ye, Wenbin;  Lou, Xin
Favorite |  | TC[WOS]:4 TC[Scopus]:5 | Submit date:2021/10/28
Sparse Filter Design  Cascaded Form  L0-norm Minimization  Forth-and-back Search.  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite |  | TC[WOS]:22 TC[Scopus]:25 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Page: 344-355
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.;  Ortmanns, M.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Quantization (Signal)  Topology  Multi-stage Noise Shaping  Delays  Wideband  Calibration  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:17 TC[Scopus]:18 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
Energy Optimized Sub-threshold VLSI Logic Family with Unbalanced Pull-up/down Network and Inverse-Narrow-Width Techniques Journal article
IEEE Transactions on Very large scale integration systems, 2015,Page: 3119-3123
Authors:  Li, M.;  Ieong, C. I.;  Law, M. K.;  Mak, P. I.;  Vai, M. I.;  Pun, S. H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/24
CMOS  Electrocardiography (ECG)  device sizing  finite impulse response (FIR) filter  inverse-narrow-width (INW)  logical effort  process-voltage-temperature (PVT) variations  sub-threshold standard logic library  ultra-low-energy  ultra-low-voltage  
Energy Optimized Subthreshold VLSI Logic Family with Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015,Volume: 23,Issue: 12,Page: 3119-3123
Authors:  Li M.-Z.;  Ieong C.-I.;  Law M.-K.;  Mak P.-I.;  Vai M.-I.;  Pun S.-H.;  Martins R.P.
Favorite |  | TC[WOS]:16 TC[Scopus]:21 | Submit date:2019/02/11
Cmos  Device Sizing  Electrocardiography (Ecg)  Finite Impulse Response (Fir) Filter  Inverse Narrow Width (Inw)  Logical Effort  Process-voltage-temperature (Pvt) Variations  Subthreshold Standard Logic Library  Ultralow Energy  Ultralow Voltage.  
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2004,Volume: 39,Issue: 1,Page: 87-99
Authors:  U S.-P.;  Martins R.P.;  Franca J.E.
Favorite |  | TC[WOS]:2 TC[Scopus]:16 | Submit date:2019/02/11
Autozeroing  Bandpass  Cmos Analog Integrated Circuits  Direct-digital Synthesis  Filters  Frequency-translated Filtering  Interpolation  Multirate Signal Processing  Sampled Data Circuits  Signal Sampling/reconstruction  Switched-capacitor Filters