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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review
Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:
Guo, Mingqiang
;
Sin, Sai Weng
;
Qi, Liang
;
Xu, Dengke
;
Wang, Guoxing
;
Martins, Rui P.
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TC[WOS]:
0
TC[Scopus]:
0
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Submit date:2022/05/17
Adc
Background
Bandwidth
Calibration
Calibration.
Clocks
Finite Impulse Response Filters
Time-interleaved
Timing
Timing Mismatch
Tuning
Very Large Scale Integration
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications
Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:
Rui P. Martins
;
Pui-In Mak
;
Sai-Weng Sin
;
Man-Kay Law
;
Yan Zhu
;
Yan Lu
;
Jun Yin
;
Chi-Hang Chan
;
Yong Chen
;
Ka-Fai Un
;
Mo Huang
;
Minglei Zhang
;
Yang Jiang
;
Wei-Han Yu
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TC[WOS]:
0
TC[Scopus]:
0
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Submit date:2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration
Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:
Guo,Mingqiang
;
Mao,Jiaji
;
Sin,Sai Weng
;
Wei,Hegong
;
Martins,Rui P.
Adobe PDF
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TC[WOS]:
30
TC[Scopus]:
34
|
Submit date:2021/03/04
Analog-to-digital Converter (Adc)
Digital Background Calibration
Split Adc
Time-interleaved (Ti) Adc
Timing-skew Mismatch
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 10,Page: 1380-1384
Authors:
Mao, Jiaji
;
Guo, Mingqiang
;
Sin, Sai-Weng
;
Martins, Rui Paulo
Adobe PDF
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TC[WOS]:
7
TC[Scopus]:
7
|
Submit date:2018/10/30
Analog-to-digital Conversion
Digital Background Calibration
Pipelined Adc
Split Adc
Opamp-sharing Technique
A 14-Bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 10,Page: 1380-1384
Authors:
Mao J.
;
Guo M.
;
Sin S.-W.
;
Martins R.P.
Favorite
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TC[WOS]:
7
TC[Scopus]:
7
|
Submit date:2019/02/11
Analog-to-digital Conversion
Digital Background Calibration
Opamp-sharing Technique
Pipelined Adc
Split Adc
A 4.2mW 77.1dB-SNDR 5MHz-BW DT 2-1 MASH ΔΣ Modulator with Multirate Opamp Sharing
Journal article
IEEE Transactions on Circuits and Systems I - Regular Papers, 2017,Page: 2641-2654
Authors:
Qi, L.
;
Sin, W.
;
U, S.P.
;
Maloberti, F.
;
Martins, R. P.
Favorite
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TC[WOS]:
0
TC[Scopus]:
0
|
Submit date:2022/01/24
Analog-to-digital Converter (Adc)
Discrete-time (Dt) Delta Sigma (Δς) Modulator
Multi-stage Noise Shaping (Mash)
Wideband
Power-efficient
Opamp Sharing
Multirate
Sar Quantizer
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Delta Sigma Modulator With Multirate Opamp Sharing
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 10,Page: 2641-2654
Authors:
Liang Qi
;
Sai-Weng Sin
;
Seng-Pan, U.
;
Franco Maloberti
;
Rui Paulo Martins
Favorite
|
|
TC[WOS]:
22
TC[Scopus]:
28
|
Submit date:2018/10/30
Analog-to-digital Converter (Adc)
Discrete-time (Dt) Delta Sigma (Delta Sigma) Modulator
Multi-stage Noise Shaping (Mash)
Wideband
Power-efficient
Opamp Sharing
Multirate
Successive Approximation Register (Sar) Quantizer
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique
Conference paper
2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, France, 17-21 Sept. 2012
Authors:
Rui Wang
;
U-Fat Chio
;
Sai-Weng Sin
;
Seng-Pan U
;
Zhihua Wang
;
Rui Paulo Martins
Favorite
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TC[WOS]:
0
TC[Scopus]:
15
|
Submit date:2019/02/11
Sar Adc
Pipelined
Digital Calibration
Op-amp Sharing