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CRYSTAL GROWTH, CHARACTERIZATION AND NEUTRON SCATTERING STUDIES OF FRUSTRATED SRRE2O4 (RE = RARE EARTH) COMPOUNDS Thesis
University of Macau: University of Macau, 2022
Authors:  Si Wu;  Li HF(李海峰)
Adobe PDF | Favorite |  | Submit date:2022/08/15
Experimental Investigation of Heat Transfer and Pressure Drop Characteristics for Vertical Downflow using Traditional and 3D-printed Mini tubes Conference paper
Xi an, China, 2022.07.27-2022.07.31
Authors:  J.H. Chen;  L.M. Tam;  A.J. Ghajar
Adobe PDF | Favorite |  | TC[WOS]:28 TC[Scopus]:0 | Submit date:2022/08/30
Heat Transfer  Pressure Drop  3d Printed Mini Tube  
A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique Journal article
IEEE Transactions on Microwave Theory and Techniques, 2022,Volume: 70,Issue: 5,Page: 2642-2657
Authors:  Liang, Yuan;  Boon, Chirn Chye;  Qi, Gengzhen;  Dziallas, Giannino;  Kissinger, Dietmar;  Ng, Herman Jalli;  Mak, Pui In;  Wang, Yong
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2022/05/17
Bicmos  Exclusive-or (Xor) Gate  Frequency Detector  Harmonic Cancellation  Jitter  Lock Detector  Mixers  Oscillators  Phase Detector (Pd)  Phase Frequency Detectors  Phase Locked Loops  Phase Noise  Phase Noise  Phase-locked Loop (Pll)  Terahertz (Thz).  Topology  Voltage-controlled Oscillators  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 196-206
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Capacitance  Clocks  Delays  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Loading  Logic Gates  Mismatch  Monte Carlo Methods  Noise Shaping  Phase Frequency Detectors  Phase/frequency Detector (Pfd)  Self Calibration  Time-to-digital Converter (Tdc).  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 51-63
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:4 TC[Scopus]:3 | Submit date:2021/09/20
Adpll  Bandwidth  Bluetooth Le (bLe)  Circuit Stability  Dco  Dtc  Fractional-n Pll  Gain  Inverse-class-f  Jitter  Low Power  Oscillators  Phase Locked Loops  Phase Noise (Pn)  Quantization (Signal)  Tdc  The Iot.  
A Half-Tangent Phase-Locked Loop for Variable-Frequency Grids of More Electric Aircraft Journal article
IEEE Transactions on Industrial Electronics, 2022
Authors:  Li, Guangqi;  Dai, Zhiyong;  Wu, Bingxuan;  Yang, Yongheng;  Huang, Jin;  Lam, Chi Seng
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Aerospace Electronics  Frequency Estimation  Half-tangent Phase-locked Loop  Large Signal Model  Phase Locked Loops  Phase Portrait  Power Electronics  Steady-state  Varying Frequency Grid  Voltage  Voltage-controlled Oscillators  
Expert vs. Influencer: Philosophy Presented under Conditions of Second-Order Observation Journal article
Human Affairs, 2021,Volume: 31,Issue: 4,Page: 470-478
Authors:  Moeller, Hans-Georg;  O/Neill, Rory;  Chiang, Hio Fai
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Academic System, Peer Review, Social Media, Youtube, Second-order Observation, Niklas Luhmann  
Multiplying DLLs Book chapter
出自: Phase-Locked Frequency Generation and Clocking:Institution of Engineering and Technology, 2020, 页码: 645-664
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/03
Clocks  Delay Lock Loops  Jitter  Low-power Electronics  Multiplying Circuits  System-on-chip  Voltage-controlled Oscillators  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Page: 3307-3316
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.;  Ieong, C. -I.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling