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A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022,Volume: 30,Issue: 2,Page: 238-242
Authors:  Yang, Zunsong;  Chen, Yong;  Yuan, Jia;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/03/04
Binary Frequency Shift Keying (Bfsk)  Frequency-locked Loop (Fll)  Integer-n  Phase Detector (Pd)  Phase Noise (Pn)  Phase-locked Loop (Pll)  Push-pull  Reference (Ref) Spur  Sub-sampling (Ss)  Voltage-controlled Oscillator (Vco)  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 2,Page: 495-505
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Yin, Jun;  Mak, Pui In
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2022/03/04
Clocks  Delays  Jitter  Performance Evaluation  Phase Noise  Topology  Voltage-controlled Oscillators  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 196-206
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Capacitance  Clocks  Delays  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Loading  Logic Gates  Mismatch  Monte Carlo Methods  Noise Shaping  Phase Frequency Detectors  Phase/frequency Detector (Pfd)  Self Calibration  Time-to-digital Converter (Tdc).  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 51-63
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2021/09/20
Adpll  Bandwidth  Bluetooth Le (bLe)  Circuit Stability  Dco  Dtc  Fractional-n Pll  Gain  Inverse-class-f  Jitter  Low Power  Oscillators  Phase Locked Loops  Phase Noise (Pn)  Quantization (Signal)  Tdc  The Iot.  
A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique Journal article
IEEE Transactions on Microwave Theory and Techniques, 2022
Authors:  Liang, Yuan;  Boon, Chirn Chye;  Qi, Gengzhen;  Dziallas, Giannino;  Kissinger, Dietmar;  Ng, Herman Jalli;  Mak, Pui In;  Wang, Yong
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2022/05/17
BiCMOS  exclusive-OR (XOR) gate  frequency detector  harmonic cancellation  jitter  lock detector  Mixers  Oscillators  phase detector (PD)  Phase frequency detectors  Phase locked loops  Phase noise  phase noise  phase-locked loop (PLL)  terahertz (THz).  Topology  Voltage-controlled oscillators  
A Half-Tangent Phase-Locked Loop for Variable-Frequency Grids of More Electric Aircraft Journal article
IEEE Transactions on Industrial Electronics, 2022
Authors:  Li, Guangqi;  Dai, Zhiyong;  Wu, Bingxuan;  Yang, Yongheng;  Huang, Jin;  Lam, Chi Seng
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Aerospace electronics  Frequency estimation  Half-tangent phase-locked loop  large signal model  Phase locked loops  phase portrait  Power electronics  Steady-state  varying frequency grid  Voltage  Voltage-controlled oscillators  
A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3093-3097
Authors:  Huang, Yunbo;  Chen, Yong;  Jiao, Hailong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2021/09/20
Cmos  Narrow Pulse Shielding  Reference (Ref) Feedthrough Suppression  Sampling Phase-locked Loop (S-pll)  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos Journal article
Electronics (Switzerland), 2021,Volume: 10,Issue: 16
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian;  Lu, Dechao;  Zhou, Lei;  Wu, Jin;  Liu, Xinyu
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2021/10/28
Cmos  Feed-forward Equalizer (Ffe)  High-speed Serial Interface  Phase-locked Loop (Pll)  Transmitter (Tx)  Voltage-controlled Oscillator (Vco)  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II