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A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems Journal article
Analog Integrated Circuits and Signal Processing, 2022,Volume: 111,Issue: 1,Page: 35-43
Authors:  Pakkirisami Churchill, Kishore Kumar;  Ramiah, Harikrishnan;  Chong, Gabriel;  Ahmad, Mohd Yazed;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/04
Charge Pump  Dc-to-dc Conversion  Dynamic Voltage Frequency Scaling (Dvfs)  Energy Harvesting  Ring-voltage ContRolled Oscillator (Ro)  
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 2,Page: 495-505
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Yin, Jun;  Mak, Pui In
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2022/03/04
Clocks  Delays  Jitter  Performance Evaluation  Phase Noise  Topology  Voltage-controlled Oscillators  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
A Time-Domain CMOS Temperature Sensor Using Gated Ring Oscillator with Linearity Optimization Conference paper
ISSCS 2021 - International Symposium on Signals, Circuits and Systems, Lasi, 15-16 July 2021
Authors:  Liu, Yangyang;  Lei, Yu;  Law, Man Kay;  Veigas, Bruno;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Bjt  Cmos Temperature Sensor  Gated Ring Oscillator  Linearity Optimization  Time Domain  
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021,Page: 1665-1669
Authors:  Wu, J.;  Leong, H. M.;  Jiang, Y.;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
CMOS  driver  fast transition  fully integrated  high-voltage (HV)  hybrid  pulse-frequency modulation (PFM)  switched-capacitor (SC)  voltage multiplier  
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase Conference paper
IEEE MTT-S International Microwave Symposium Digest, Atlanta, GA, USA, 7-25 June 2021
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Zheng, Xuqiang;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
Bang-bang Clock And Data Recovery (Bbcdr)  Clock Selection  Cmos  Frequency Acquisition  Frequency Detector (Fd)  Reference (Ref)  Ring Oscillator (Ro)  Strobe Point (Sp)  
A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s reference-less FD-less BBCDR using a deliberately-clock-selected strobe point based on a 2π/3-interval phase Conference paper
WE02G
Authors:  Zhao, X.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
CDR  CMOS  Reference  
A 0.003-mm2440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 6,Page: 2307-2316
Authors:  Yang, Zunsong;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/09/20
CMOS  current-reuse sampling phase detector (CRS-PD)  integrated jitter  loop filter (LF)  master-slave sampling filter (MSSF)  master-slave sampling phase detector (MSS-PD)  phase noise (PN)  Phase-locked loop (PLL)  reference spur  ring voltage-controlled oscillator (VCO)  type-I  type-II  
A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3866-3879
Authors:  Zhao,Qiang;  Zheng,Wenhan;  Zhao,Xiaojin;  Cao,Yuan;  Zhang,Feng;  Law,Man Kay
Favorite |  | TC[WOS]:14 TC[Scopus]:13 | Submit date:2021/03/11
Dynamic Entropy Source  Full Reconfigurability  High Reliability  Physical Unclonable Function  Resistive Random Access Memory  True Random Number Generator  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:4 TC[Scopus]:3 | Submit date:2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)