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A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3753-3763
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Page: 3307-3316
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.;  Ieong, C. -I.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
16.3 A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation over PVT Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Yang,Xiaofeng;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:6 | Submit date:2021/03/09
A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT Conference paper
Proceeding of 2019 IEEE International Solid- State Circuits Conference - (ISSCC)
Authors:  Yang, X.;  Chan, C. H.;  Zhu, Y.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Phase locked loops  Jitter  Clocks  Phase noise  Wideband  Frequency locked loops  
A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 2,Page: 157-161
Authors:  Jiang T.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:6 TC[Scopus]:4 | Submit date:2019/02/14
Bootstrap (Bt)  Low Voltage  Non-overlapping Clock  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019,Page: 88-98
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/24
Clock multiplier  digital-controlled delay line (DCDL)  frequency-tracking loop (FTL)  injection-locked phase-locked loop (IL-PLL)  multiplying delay-locked loop (MDLL)  phase noise  ring voltage-controlled oscillator (RVCO)  root-mean-square (rms) jitter  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 1,Page: 88-98
Authors:  Yang S.;  Yin J.;  Mak P.-I.;  Martins R.P.
Favorite |  | TC[WOS]:19 TC[Scopus]:19 | Submit date:2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A Time-Interleaved Ring-VCO with Reduced 1/f Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits (JSSC), 2016,Page: 2979-2991
Authors:  Yin, J.;  Mak, P. I.;  Maloberti, F.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/24
Ring voltage-controlled oscillator (RVCO)  time-interleaved (TI)  impulse sensitivity function (ISF)  phase noise  1/f3 phase noise corner  phase combiner  divided output  supply voltage  flicker noise  
A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output Journal article
IEEE Journal of Solid-State Circuits, 2016,Volume: 51,Issue: 12,Page: 2979-2991
Authors:  Yin J.;  Mak P.-I.;  Maloberti F.;  Martins R.P.
Favorite |  | TC[WOS]:20 TC[Scopus]:20 | Submit date:2019/02/11
1/f3 Phase Noise Corner  Divided Output  Flicker Noise  Impulse Sensitivity Function (Isf)  Phase Combiner  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Supply Voltage  Time-interleaved (Ti).