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A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer Journal article
Electronics (Switzerland), 2022,Volume: 11,Issue: 12
Authors:  Xu, Zhuofan;  Hu, Biao;  Wu, Tianxiang;  Yao, Yuting;  Chen, Yong;  Ren, Junyan;  Ma, Shunli
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2022/08/02
Asynchronous Sar Adc  Input Pga  Rv-buffer  Split Cdac  
English textbook selection in Taiwan: Voices of two book sales representatives Journal article
Education Research International, 2022,Volume: 2022,Page: 1-6
Authors:  Barry Lee Reynolds;  Xuan Van Ha;  Melissa H. Yu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/06/07
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 745-756
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC Conference paper
Proceeding of 2021 Symposium on VLSI, N/A, 2021-06-15
Authors:  Wei, L.;  Zheng, Z.;  Markulic, N.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, 13-19 June 2021
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Proceedings - International SoC Design Conference 2021, ISOCC 2021, Jeju Island, Korea, Republic of, 06-09 October 2021
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2022/05/13
Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite |  | TC[WOS]:8 TC[Scopus]:10 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch