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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing Conference paper
Proceedings of the Custom Integrated Circuits Conference, Newport Beach, CA, USA, 24-27 April 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xiao, Gangjun;  Martins, Rui P.
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Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
IEEE Open Journal of the Solid-State Circuits Society, 2021,Page: 129-139
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, 13-19 June 2021
Authors:  Zhang, Minglei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
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Background  Input Independent  Time Domain Adc  Time-interleaved Adc  Timing Skew Calibration  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:11 TC[Scopus]:9 | Submit date:2021/03/04
Analog-to-digital Converter  Background Timing Skew Calibration  Current Integrating Sampler  Sar Adc  Time-interleaved Adc  Timing Skew  
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Proceedings - International SoC Design Conference 2021, ISOCC 2021, Jeju Island, Korea, Republic of, 06-09 October 2021
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Martins, Rui P.
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Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, JUN 16-19, 2020, ELECTR NETWORK
Authors:  Jiang,Dongyang;  Qi,Liang;  Sin,Sai Weng;  Maloberti,Franco;  Martins,R. P.
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A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Mingqiang Guo;  Jiaji Mao;  Sai-Weng Sin;  Hegong Wei;  Rui P. Martins
Favorite |  | TC[WOS]:22 TC[Scopus]:25 | Submit date:2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch  
A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Page: 693-705
Authors:  Guo, M.;  Mao, J.;  Sin,SS. W.;  Wei, H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Calibration  Timing  Clocks  Impedance  Signal To Noise Ratio  Channel Estimation  Jitter