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LDO-free Power Management System – Delta-Sigma Modulator ADC Directly Powered by Boost-up DC-DC Converter Project
项目编号: MYRG2020-00013-IME, 2022-
Authors:  TERRYSSW
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/02/16
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 64-74
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
Wideband Continuous-time MASH Delta-Sigma Modulators: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Qi, Liang;  Liu, Yuekai;  Sin, Sai Weng;  Xing, Xinpeng;  Wang, Guoxing;  Ortmanns, Maurits;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/05/17
Continuous-time (Ct)  Delays  Delta-sigma Modulator (Dsm)  Feature Extraction  Multi-stage Noise Shaping  Multi-stage Noise-shaping (Mash)  Qn Extraction.  Qn Leakage  Quantization (Signal)  Quantization Noise (Qn)  Sturdy Mash  Topology  Wideband  Wireless Communication  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
IEEE Open Journal of the Solid-State Circuits Society, 2021,Page: 129-139
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
Discrete-time mash delta-sigma modulator with second-order digital noise coupling for wideband high-resolution applications Conference paper
Proceedings - IEEE International Symposium on Circuits and Systems
Authors:  Qin, Xinyu;  Zhang, Jingying;  Qi, Liang;  Sin, Sai Weng;  Martins, Rui P.;  Wang, Guoxing
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date：2021/09/20
Digital noise coupling  Multistage noise shaping (MASH)  Noise leakage  Wideband high-resolution applications  ΔΣ modulator (DSM)  
Near-Optimal Decoding of Incremental Delta-Sigma ADC Output Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2020,Volume: 67,Issue: 11,Page: 3670-3680
Authors:  Wang,Bo;  Law,Man Kay;  Belhaouari,Samir Brahim;  Bermak,Amine
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date：2021/03/11
Decimation Filter  Delta-sigma Modulator  Idc  Incremental Adc  Noise Penalty Factor  Optimal Filter  Reconstruction Filter  Thermal Noise Averaging  
On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback Conference paper
IEEE International Symposium on Circutis and Systems (2020)
Authors:  Wang, B.;  Law, M. K.;  Bermak, A.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/08/01
Incremental Delta-Sigma Analog-to-Digital Converter  Fully Differential IDC  1.5-bit Feedback  Modulator Codeword  Time-Domain Analysis  
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date：2020/12/04
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ct-dsm)  Preliminary Sampling And Quantization (Psq) Technique  Single Amplifier Biquad (Sab)  Successiveapproximation-register (Sar) Architecture-based Quantizer (Qtz)  
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, JUN 16-19, 2020, ELECTR NETWORK
Authors:  Jiang,Dongyang;  Qi,Liang;  Sin,Sai Weng;  Maloberti,Franco;  Martins,R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:8 | Submit date：2021/03/04