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A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 767-780
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang;  Li, Guike;  Zhang, Zhao;  Liu, Jian;  Wu, Nanjian;  Liu, Liyuan;  Chen, Yong;  Xiao, Xi;  Qi, Nan
Favorite |  | TC[WOS]:6 TC[Scopus]:3 | Submit date:2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 2,Page: 546-561
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:3 TC[Scopus]:2 | Submit date:2021/10/28
Acquisition Speed  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Clocks  Cmos  Detectors  Four-level Pulse Amplitude Modulation (Pam-4)  Frequency Detector (Fd)  Frequency Modulation  Hybrid Control Circuit (Hcc)  Jitter  Jitter Tolerance (Jtol)  Jitter Transfer Function (Jtf)  Logic Gates  Phase Detector (Pd)  Strobe Point (Sp).  Switches  Voltage-controlled Oscillators  
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1358-1371
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Wang, Lin;  Mak, Pui In;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:1 | Submit date:2022/05/13
And Zero Net Current (Znc)  Bang-bang Clock And Data Recovery (Bbcdr)  Charge Pump (Cp)  Cmos  Four-level Pulse-amplitude Modulation (Pam)  Frequency Detector (Fd)  Half-rate  Negative Net Current (Nnc)  Positive Net Current (Pnc)  Reference-less  
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
Authors:  He, Jian;  Lu, Donglai;  Xue, Haiyun;  Chen, Sikai;  Liu, Han;  Li, Leliang;  Li, Guike;  Zhang, Zhao;  Liu, Jian;  Liu, Liyuan;  Wu, Nanjian;  Yu, Ningmei;  Liu, Fengman;  Xiao, Xi;  Chen, Yong;  Qi, Nan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/05
400gbase-sr8  Continuous-time Linear Equalizer (Ctle)  Four-level Pulse Amplitude Modulation (Pam-4)  Integrated Circuit Modeling  Nonlinear Optics  Optical Receivers  Optical Superlattices  Optical Transmitters  Sige Bicmos  Trans-impedance Amplifier (Tia)  Transceiver (Trx)  Transceivers  Vertical Cavity Surface Emitting Lasers  Vertical-cavity-surface-emitting Laser (Vcsel) Driver  
A 1.4-Vppd64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS Conference paper
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings, Grenoble, France, 13-22 Sept. 2021
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian;  Zhou, Lei;  Wu, Jin;  Liu, Xinyu
Favorite |  | TC[WOS]:1 TC[Scopus]:4 | Submit date:2021/12/08
100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects Conference paper
2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021
Authors:  Lu, Donglai;  He, Jian;  Li, Weizhong;  Chen, Sikai;  Liu, Jian;  Wu, Nanjian;  Yu, Ningmei;  Liu, Liyuan;  Chen, Yong;  Xiao, Xi;  Qi, Nan
Favorite |  | TC[WOS]:2 TC[Scopus]:1 | Submit date:2022/05/13
400GBASE-SR8  four-level pulse amplitude modulation (PAM-4)  trans-impedance amplifier (TIA)  vertical-cavity-surface-emitting laser (VCSEL) driver  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:10 TC[Scopus]:2 | Submit date:2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Proceedings of the Custom Integrated Circuits Conference, Boston, MA, USA, 22-25 March 2020
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:7 | Submit date:2021/03/04
Acquisition Speed  Alexander Phase Detector (Pd)  Bang-bang  Bang-bang Clock And Data Recovery (Cdr)  Charge Pump (Cp)  Frequency Detector (Fd)  Full-rate  Jitter Tolerance (Jtf)  Jitter Transfer Function (Jtf)  Single Loop  Strobe Point (Sp)  
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS Conference paper
Session 20: High-Speed Wireline Transceivers
Authors:  Zhao, X.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Single loop  full-rate  bang-bang  bang-bang clock and recovery circuit  
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 12,Page: 4850-4861
Authors:  Fan,Chao;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:3 | Submit date:2021/03/09
Cmos  Current-mode-logic (Cml) Driver  Feed-forward Equalization (Ffe)  Four-level Pulse-amplitude Modulation (Pam-4)  Source-series-terminated (Sst) Driver  Sst-cml-hybrid (Sch) Driver  Transmitter (Tx)