UM

Browse/Search Results:  1-3 of 3 Help

Selected(0)Clear Items/Page:    Sort:
A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB Conference paper
San Francisco, 2022-02
Authors:  MAK, Pui-In;  SHAO, Haijun;  QI, Gengzhen;  MARTINS, Rui
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/07
Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors:  Yang X.;  Zhu Y.;  Chan C.-H.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:6 TC[Scopus]:7 | Submit date:2019/02/11
Isf  Low Clock Jitter Circuit  Self-bias  
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017,Volume: 64,Issue: 11,Page: 2844-2857
Authors:  Yu, Wei-Han;  Peng, Xingqiang;  Mak, Pui-In;  Martins, Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2018/10/30
Aa Battery  Antenna Impedance Mismatch  Class-d  Cmos  Digital Am Modulation  Dynamic Matching Network (Dmn)  Error-vector Magnitude (Evm)  Inverter Chain  Leakage Current  Matching Network (Mn)  Polar  Power Amplifier (Pa)  Power-added Efficiency (Pae)  Power Gating