UM

Browse/Search Results:  1-10 of 24 Help

Selected(0)Clear Items/Page:    Sort:
A 108-nW 0.8-mm 2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 11,Page: 1-10
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/07/22
Approximate Computing  Convolutional Neural Network (Cnn)  Feature Extraction  Keyword Spotting (Kws)  Quantization  Reconfigurable  Sparsity  Switched-capacitor Circuits  Voice Activity Detection (Vad)  
Enhanced antibacterial function of a supramolecular artificial receptor-modified macrophage (SAR-Macrophage) Journal article
Materials horizons, 2022,Volume: 9,Issue: 3,Page: 934-941
Authors:  Cheng, Qian;  Xu, Meng;  Sun, Chen;  Yang, Kuikun;  Yang, Zhiqing;  Li, Junyan;  Zheng, Jun;  Zheng, Ying;  Wang, Ruibing
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2022/03/28
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2019,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:11 TC[Scopus]:10 | Submit date:2021/03/09
Cmos  Divider-by-4  Dual Loop  Dynamic Latch  Figure-of-merit (Fom)  Frequency Detector (Fd)  Millimeter (Mm)-wave  Phase Detector (Pd)  Phase-locked Loop (Pll)  Voltage-controlled Oscillator (Vco)  Voltage-to-current Converter (Vic)  
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 10,Page: 3991-4004
Authors:  Chen,Yong;  Mak,Pui In;  Yang,Zunsong;  Boon,Chirn Chye;  Martins,Rui P.
Favorite |  | TC[WOS]:7 TC[Scopus]:6 | Submit date:2021/03/09
Active Inductor (Ai)  Bandwidth (Bw) Extension  Cmos  Current Reuse  Current-mode Logic (Cml)  Current-mode Transmitter  Data-dependent Jitter (Ddj)  Figure-of-merit (Fom)  Flip-flop (Ff)  Fractional De-emphasis (De)  Hybrid Delay Line  Latch  Pulse-width-modulated (Pwm)  Unit Interval (Ui)  
A 0.0018-mm2 153% locking-range CML-Based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-gm Cell Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3330-3339
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:8 TC[Scopus]:8 | Submit date:2021/03/09
5g New Radio  Cmos  Current-mode-logic (Cml)  Divider-by-2  Injection Locking  Latch  Locking Range (Lr)  Negative-gm (Ng)  Phasor Diagram  Self-resonant Frequency (Fsr)  Sensitivity Curve (Sc)  Shunt Peaking  
A 6.5x7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz) Journal article
IEEE SOLID-STATE CIRCUITS LETTERS, 2019,Page: 37-40
Authors:  Chen, Y.;  Yang, Z.;  Zhao, X.;  Huang, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Frequency divider  locking range (LR)  5G radio band  self-oscillationmode (SOM)  phase noise  non-self-oscillation-mode (NSOM)  
A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz) Journal article
IEEE Solid-State Circuits Letters, 2019,Volume: 2,Issue: 5,Page: 37-40
Authors:  Chen,Yong;  Yang,Zunsong;  Zhao,Xiaoteng;  Huang,Yunbo;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:13 TC[Scopus]:16 | Submit date:2021/03/09
5g Bands  Current-mode-logic (Cml)  Figure-of-merit (Fom)  Frequency Divider  Locking Range (Lr)  Non-self-oscillation-mode (Nsom)  Phasor  Self-oscillation-mode (Som)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Delta Sigma Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Conference paper
Authors:  Wang, Wei;  Zhu, Yan;  Chan, Chi-Hang;  Martins, Rui Paulo
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2018/10/30
Terms-Analog-to-digital conversion (ADC)  continuous-time (CT) delta-sigma modulator  DAC driver  passive integrator  single amplifier biquad (SAB)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 10,Page: 2783-2794
Authors:  Wang W.;  Zhu Y.;  Chan C.-H.;  Martins R.P.
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2019/02/11
Analog-to-digital conversion (ADC)  continuous-time (CT) delta-sigma modulator  DAC driver  passive integrator  single amplifier biquad (SAB)  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2018,Volume: 53,Issue: 10,Page: 2783-2794
Authors:  Wang,Wei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2019/08/22
Analog-to-digital conversion (ADC)  continuous-time (CT) delta-sigma modulator  DAC driver  passive integrator  single amplifier biquad (SAB)