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A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer Journal article
Electronics (Switzerland), 2022,Volume: 11,Issue: 12
Authors:  Xu, Zhuofan;  Hu, Biao;  Wu, Tianxiang;  Yao, Yuting;  Chen, Yong;  Ren, Junyan;  Ma, Shunli
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/02
Asynchronous Sar Adc  Input Pga  Rv-buffer  Split Cdac  
English Textbook Selection in Taiwan: Voices of Two Book Sales Representatives Journal article
Education Research International, 2022,Volume: 2022
Authors:  Barry Lee Reynolds;  Xuan Van Ha;  Melissa H. Yu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/06/07
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 745-756
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC Conference paper
Proceeding of 2021 Symposium on VLSI
Authors:  Wei, L.;  Zheng, Z.;  Markulic, N.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Background calibration  nonlinearity  pipelined ADC  split-SAR ADC  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, 13-19 June 2021
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture Conference paper
Proceedings of the Custom Integrated Circuits Conference, ELECTR NETWORK, APR 25-30, 2021
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Zhu, Zhangming;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/09/20
A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits (Invited Special Issue of CICC), 2020,Page: 693-705
Authors:  Guo, M.;  Mao, J.;  Sin, S. W.;  Wei, H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Calibration  Timing  Clocks  Impedance  Signal to noise ratio  Channel estimation  Jitter  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Favorite |  | TC[WOS]:19 TC[Scopus]:23 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration Conference paper
Proc. of IEEE Custom Integrated Circuits Conference – CICC
Authors:  Guo, M.;  Mao, J.;  Sin, S. W.;  Wei, H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
SAR analog-to-digital converter (ADC)  time-interleaved (TI) ADC  timing-skew calibration  split ADC  background mismatch calibration