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A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Page: 344-355
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.;  Ortmanns, M.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2022/01/25
Quantization (signal)  Topology  Multi-stage noise shaping  Delays  Wideband  Calibration  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 344-355
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.;  Ortmanns,Maurits
Favorite |  | TC[WOS]:18 TC[Scopus]:16 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)