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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1480-1491
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 745-756
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter Journal article
IET Circuits, Devices and Systems, 2022,Volume: 16,Issue: 2,Page: 189-199
Authors:  Dong, Li;  Song, Yan;  Zhang, Bing;  Lan, Zhechong;  Xin, Youze;  Liu, Liheng;  Li, Ken;  Wang, Xiaofei;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/03/28
Analog-to-digital Converter  Dynamic Element Matching  Successive Approximation Register  Time-based Integral Error  Total Harmonic Distribution  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun;  Chen, Yong;  Yu, Qi
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
IEEE Open Journal of the Solid-State Circuits Society, 2021,Page: 129-139
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Microelectronics Journal, 2021,Volume: 113
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken;  Jing, Xixin;  Zhang, Bing;  Gui, Xiaoyan;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
IEEE Access, 2021,Volume: 9,Page: 77545-77554
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong;  Ma, Shunli;  Ye, Fan;  Ren, Junyan
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/10/28
Asynchronous Logic  Cmos  Customized Unit Capacitor  Figure-of-merit (Fom)  Split-cdac  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:11 TC[Scopus]:9 | Submit date:2021/03/04
Analog-to-digital Converter  Background Timing Skew Calibration  Current Integrating Sampler  Sar Adc  Time-interleaved Adc  Timing Skew  
A Readout Circuit for Tactile Sensor with Crosstalk Suppression and Non-Uniformity Compensation Conference paper
2021 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2021 and 2021 IEEE Conference on Postgraduate Research in Microelectronics and Electronics, PRIMEASIA 2021
Authors:  Li, Yao;  Zhao, Yiqiang;  Ye, Mao;  Chen, Yong
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/13
CMOS  correlated double sampling (CDS)  crosstalk suppression  non-uniformity compensation  readout circuit  serial peripheral interface (SPI)  successive-approximation-register (SAR) analog-to-digital converter (ADC)  tactile sensor  
A 2nd-Order Noise-Shaping SAR ADC with Lossless Dynamic Amplifier Assisted Integrator Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 10,Page: 1819-1823
Authors:  Zhang, Yanbo;  Liu, Shubin;  Tian, Binbin;  Zhu, Yan;  Chan, Chi Hang;  Zhu, Zhangming
Favorite |  | TC[WOS]:11 TC[Scopus]:9 | Submit date:2021/12/06
Analog-to-digital Converter (Adc)  Dynamic Amplifier  Lossless Integrator  Lossy Integrator  Noise Shaping (Ns)  Oversampling  Ping Pong  Successive Approximation Register (Sar)