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A 108-nW 0.8-mm 2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 11,Page: 1-10
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/07/22
Approximate Computing  Convolutional Neural Network (Cnn)  Feature Extraction  Keyword Spotting (Kws)  Quantization  Reconfigurable  Sparsity  Switched-capacitor Circuits  Voice Activity Detection (Vad)  
English textbook selection in Taiwan: Voices of two book sales representatives Journal article
Education Research International, 2022,Volume: 2022,Page: 1-6
Authors:  Barry Lee Reynolds;  Xuan Van Ha;  Melissa H. Yu
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/06/07
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
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Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
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Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, 13-19 June 2021
Authors:  Zhang, Minglei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2021/09/20
Background  Input Independent  Time Domain Adc  Time-interleaved Adc  Timing Skew Calibration  
A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Volume: 68,Issue: 2,Page: 557-568
Authors:  Jiang,Wenning;  Zhu,Yan;  Chan,Chi Hang;  Murmann,Boris;  Martins,Rui Paulo
Favorite |  | TC[WOS]:11 TC[Scopus]:9 | Submit date:2021/03/04
Analog-to-digital Converter  Background Timing Skew Calibration  Current Integrating Sampler  Sar Adc  Time-interleaved Adc  Timing Skew  
On Fully Differential Incremental ΔΣ ADC With Initial Feedback Zeroing and 1.5-Bit Feedback Conference paper
IEEE International Symposium on Circutis and Systems (2020)
Authors:  Wang, B.;  Law, M. K.;  Bermak, A.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/01
Incremental Delta-Sigma Analog-to-Digital Converter  Fully Differential IDC  1.5-bit Feedback  Modulator Codeword  Time-Domain Analysis  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:11 TC[Scopus]:9 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  And Temperature (Pvt) Robustness  High-speed Adc  Metastability  Process  Supply Voltage  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)  
A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 16-20 Feb. 2020
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:12 | Submit date:2021/03/04