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A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components Journal article
Sensors (Basel, Switzerland), 2022,Volume: 22,Issue: 15
Authors:  Zhang, Mengdi;  Zhao, Ye;  Chen, Yong;  Crovetti, Paolo;  Wang, Yanji;  Ning, Xinshun;  Qiao, Shushan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/09/07
Analog-to-digital Converter (Adc)  Differential Nonlinearity (Dnl)  Effective Number Of Bits (Enob)  Fpga  Integral Nonlinearity (Inl)  Time-to-digital Converter (Tdc)  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 196-206
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:2 TC[Scopus]:1 | Submit date:2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Capacitance  Clocks  Delays  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Loading  Logic Gates  Mismatch  Monte Carlo Methods  Noise Shaping  Phase Frequency Detectors  Phase/frequency Detector (Pfd)  Self Calibration  Time-to-digital Converter (Tdc).  
A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
Authors:  Mao, Xiangyu;  Lu, Yan;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/09/09
Calibration  Codes  Digital  Distributed Power Delivery  Dynamic Voltage And Frequency Scaling (Dvfs)  Fully-integrated Voltage Regulator (Fivr)  Hybrid Control  Hybrid Power Systems  Low-dropout Regulator (Ldo)  Power Transistors  Quantization (Signal)  Thermometers  Voltage Control  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 1,Page: 51-63
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.;  Staszewski, Robert Bogdan
Favorite |  | TC[WOS]:4 TC[Scopus]:2 | Submit date:2021/09/20
Adpll  Bandwidth  Bluetooth Le (bLe)  Circuit Stability  Dco  Dtc  Fractional-n Pll  Gain  Inverse-class-f  Jitter  Low Power  Oscillators  Phase Locked Loops  Phase Noise (Pn)  Quantization (Signal)  Tdc  The Iot.  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction Conference paper
IEEE International Symposium on Circutis and Systems (2020), ELECTR NETWORK, OCT 10-21, 2020
Authors:  Xu, C.;  Zhang, J.;  Law, M. K.;  Zhao, X.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Multiplier  Multi-bit  Physical Unclonable Function  Path Delay Extraction  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:11 TC[Scopus]:10 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  And Temperature (Pvt) Robustness  High-speed Adc  Metastability  Process  Supply Voltage  Time Interpolation  Time Residue  Time-domain Adc  Time-to-digital Converter (Tdc)  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 12,Page: 3396-3409
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:13 TC[Scopus]:15 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  And Temperature (Pvt) Robustness  Low Power Supply  Process  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage  Voltage-to-time Converter (Vtc)  
529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers
Authors:  Chen, P.;  Meng, X.;  Yin, J.;  Mak, P. I.;  Martins, R. P.;  Staszewski, R. B.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
ADPLL  Bluetooth LE (BLE)  DCO  fractionalN PLL  phase noise (PN)  TDC  DTC  inverse-class-F  low power  the IoT