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Document Type：Journal article
Date Issued：2017
Faculties：FST
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Language：英語English
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Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial V-cm-Based Switching
Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017,Volume: 25,Issue: 3,Page: 1168-1172
Authors:
Xing, Dezhi
;
Zhu, Yan
;
Chan, Chi-Hang
;
Sin, Sai-Weng
;
Ye, Fan
;
Ren, Junyan
;
U, Seng-Pan
;
Martins, Rui Paulo
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TC[WOS]:
11
TC[Scopus]:
15
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Submit date：2018/10/30
Common Mode Variation
Partial V-cm-based Switching
Time-interleaved Successive ApproximaTion Register Analog-to-digital Converter (Ti Sar Adc)
