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A 2.63 μw ECG Processor with Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device Journal article
IEEE Transactions on Biomedical Circuits and Systems, 2021,Volume: 15,Issue: 4,Page: 777-790
Authors:  Yin, Yue;  Abubakar, Syed Muhammad;  Tan, Songyao;  Shi, Jiahua;  Yang, Peilin;  Yang, Wendi;  Jiang, Hanjun;  Wang, Zhihua;  Jia, Wen;  Ua, Seng Pan
Favorite |  | TC[WOS]:6 TC[Scopus]:11 | Submit date：2021/12/08
Adaptive Arrhythmia Detection  Data Compression  Ecg Processor  Implantable Cardiac Monitoring  Swinging Door Trending  
SE5: Making a Career Choice Other
2021-02-13
Authors:  Daly, Denis;  Lulec, Zeynep;  Yazicigil, Rabia Tugce;  Burdett, Alison;  Mandal, Rituparna;  Moreira, Matheus;  Muratore, Dante;  Walcott-Bryant, Aisha;  Seng-Pang Ben, U.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/12/07
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, JUN 18-22, 2018
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  MartinMartinss R.P.
Favorite |  | TC[WOS]:21 TC[Scopus]:7 | Submit date：2019/02/11
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors:  Xing D.;  Zhu Y.;  Chan C.-H.;  Maloberti F.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/11
Reference Interference  Sar Adc  Time-interleaved Scheme  Two-step Sar Conversion  
Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors:  Liu J.;  Chan C.-H.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date：2019/02/13
Bandwidth Mismatches  Split-digital To Analog Converter (Dac)  Successive-approximation-register (Sar) Analog-to-digital Converter (Adc)  Time-interleaved (Ti)  Variance Based  Window Detector (Wd)  
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Tainan, TAIWAN, NOV 05-07, 2018
Authors:  Jiang W.;  Zhu Y.;  Chan C.-H.;  Murmann B.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:4 TC[Scopus]:5 | Submit date：2019/02/11
Background Calibration  Current Integrating Sampler  Time-interleaved Adc  Timing Skew  
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018, Hsinchu, TAIWAN, APR 16-19, 2018
Authors:  Mao F.;  Lu Y.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date：2019/02/11
Delay Compensation  Feedback Loop  Implantable Medical Devices  Real Time  Voltage Doubler  Wireless Power Transfer  
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 3,Page: 572-583
Authors:  Qiu, Lei;  Tang, Kai;  Zheng, Yuanjin;  Siek, Liter;  Zhu, Yan;  U, Seng-Pan
Favorite |  | TC[WOS]:10 TC[Scopus]:11 | Submit date：2018/10/30
Digital Background Calibration  Subradix-2  Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)  Time Interleaved (Ti)  Time Skew  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018,Volume: 53,Issue: 3,Page: 850-860
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite |  | TC[WOS]:40 TC[Scopus]:42 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
A dual-output SC converter with dynamic power allocation for multicore application processors Conference paper
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Authors:  Jiang J.;  Lu Y.;  Liu X.;  Ki W.-H.;  Mok P.K.T.;  Seng-Pan U.;  Martins R.P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date：2019/02/11