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A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components Journal article
Sensors (Basel, Switzerland), 2022,Volume: 22,Issue: 15
Authors:  Zhang, Mengdi;  Zhao, Ye;  Chen, Yong;  Crovetti, Paolo;  Wang, Yanji;  Ning, Xinshun;  Qiao, Shushan
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/09/07
Analog-to-digital Converter (Adc)  Differential Nonlinearity (Dnl)  Effective Number Of Bits (Enob)  Fpga  Integral Nonlinearity (Inl)  Time-to-digital Converter (Tdc)  
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1480-1491
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter Journal article
IET Circuits, Devices and Systems, 2022,Volume: 16,Issue: 2,Page: 189-199
Authors:  Dong, Li;  Song, Yan;  Zhang, Bing;  Lan, Zhechong;  Xin, Youze;  Liu, Liheng;  Li, Ken;  Wang, Xiaofei;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/03/28
Analog-to-digital Converter  Dynamic Element Matching  Successive Approximation Register  Time-based Integral Error  Total Harmonic Distribution  
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Calibrations Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 745-756
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Ding, Ruixue;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2022/03/28
Analog-to-digital Converter (Adc)  Inter-stage Gain And Offset Calibrations  Noise-shaping (Ns)  Split Adc  Successive Approximation Register (Sar)-assisted Pipeline  
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 3,Page: 767-780
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang;  Li, Guike;  Zhang, Zhao;  Liu, Jian;  Wu, Nanjian;  Liu, Liyuan;  Chen, Yong;  Xiao, Xi;  Qi, Nan
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
Spectral and energy efficiency for uplink massive MIMO systems with mixed-ADC architecture Journal article
Physical Communication, 2022,Volume: 50
Authors:  Tan, Weiqiang;  Li, Shidang;  Zhou, Meng
Favorite |  | TC[WOS]:3 TC[Scopus]:3 | Submit date:2022/03/04
Analog-to-digital Converter  Energy Efficiency  Maximum Ratio Combining  Mixed Architecture  Multiuser Massive Mimo  Spectral Efficiency  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun;  Chen, Yong;  Yu, Qi
Favorite |  | TC[WOS]:6 TC[Scopus]:5 | Submit date:2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
IEEE Open Journal of the Solid-State Circuits Society, 2021,Page: 129-139
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
IEEE Journal of Solid-State Circuits, 2021,Volume: 56,Issue: 8,Page: 2375-2387
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Microelectronics Journal, 2021,Volume: 113
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken;  Jing, Xixin;  Zhang, Bing;  Gui, Xiaoyan;  Geng, Li
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry