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Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,Volume: 28,Issue: 4,Page: 1074-1078
Authors:  Sun, Jie;  Zhang, Minglei;  Qiu, Lei;  Wu, Jianhui;  Liu, Weiqiang
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date:2021/10/28
Background Calibration  Bit Weight  Dither Injection  Pipelined Sar Adc  Residue Increment  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu