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A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique Journal article
IEEE Transactions on Microwave Theory and Techniques, 2022,Volume: 70,Issue: 5,Page: 2642-2657
Authors:  Liang, Yuan;  Boon, Chirn Chye;  Qi, Gengzhen;  Dziallas, Giannino;  Kissinger, Dietmar;  Ng, Herman Jalli;  Mak, Pui In;  Wang, Yong
Favorite |  | TC[WOS]:1 TC[Scopus]:0 | Submit date:2022/05/17
Bicmos  Exclusive-or (Xor) Gate  Frequency Detector  Harmonic Cancellation  Jitter  Lock Detector  Mixers  Oscillators  Phase Detector (Pd)  Phase Frequency Detectors  Phase Locked Loops  Phase Noise  Phase Noise  Phase-locked Loop (Pll)  Terahertz (Thz).  Topology  Voltage-controlled Oscillators  
Wideband variable-gain amplifiers based on a pseudo-current-steering gain-tuning technique Journal article
IEEE Access, 2021,Volume: 9,Page: 35814-35823
Authors:  Kong, Lingshan;  Chen, Yong;  Yu, Haohong;  Boon, Chirn Chye;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2022/05/13
active inductor  CMOS  data-dependent jitter (DDJ)  dual-branch current mirror  high-speed transceiver  negative capacitance (NC)  peak-to-peak jitter  pseudo-current steering  variable-gain amplifier (VGA)  wide-tuning gain control  
A 0.024-mm245.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz Conference paper
Midwest Symposium on Circuits and Systems, Springfield, MA, USA, 9-12 Aug. 2020
Authors:  Chen,Yong;  Mak,Pui In;  Chye Boon,Chirn;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:3 | Submit date:2021/03/04
A 0.096-mm2 1-20-GHz triple-path noise- canceling common-gate common-source LNA with dual complementary pMOS-nMOS configuration Journal article
IEEE Transactions on Microwave Theory and Techniques, 2020,Volume: 68,Issue: 1,Page: 144-159
Authors:  Yu,Haohong;  Chen,Yong;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:26 TC[Scopus]:27 | Submit date:2021/03/09
Cmos  Common Gate (Cg)  Common Source (Cs)  Input Third-order Intercept Point (Iip3)  Noise Figure (Nf)  Partial Distortion Canceling  Pmos-nmos Configuration  Resistive Feedback  Triple-path And Dual-path Noise CaNceling (Nc)  Wideband Input Matching  Wideband Low-noise Amplifier (Lna)  
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, Bangkok, Thailand, 11-14 Nov. 2019
Authors:  Kong,Lingshan;  Chen,Yong;  Yu,Haohong;  Pan,Quan;  Boon,Chirn Chye;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2021/03/09
Bandwidth (Bw)  Cmos  High-speed Transceiver  Negative Capacitance  Peak-to-peak Jitter  Pseudo-current Steering  Variable-gain Amplifier (Vga)  Wide-tuning Gain Control  
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS Conference paper
Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption, Bangkok, Thailand, 11-14 Nov. 2019
Authors:  Balachandran, Arya;  Chen, Yong;  Boon, Chirn Chye
Favorite |  | TC[WOS]:0 TC[Scopus]:2 | Submit date:2021/10/28
Analog Front-end (Afe)  Channel Loss  Cmos  Continuous-time Linear Equalizer (Ctle)  Decision Feedback Equalization (Dfe)  Inductorless  Low Frequency Equalization (Lfeq)  Pseudorandom Binary Sequence (Prbs)  Receiver  
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 10,Page: 3991-4004
Authors:  Chen,Yong;  Mak,Pui In;  Yang,Zunsong;  Boon,Chirn Chye;  Martins,Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:6 | Submit date:2021/03/09
Active Inductor (Ai)  Bandwidth (Bw) Extension  Cmos  Current Reuse  Current-mode Logic (Cml)  Current-mode Transmitter  Data-dependent Jitter (Ddj)  Figure-of-merit (Fom)  Flip-flop (Ff)  Fractional De-emphasis (De)  Hybrid Delay Line  Latch  Pulse-width-modulated (Pwm)  Unit Interval (Ui)  
A 0.013-mm(2) 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS Journal article
Authors:  Balachandran, Arya;  Chen, Yong;  Boon, Chirn Chye
Favorite |  | TC[WOS]:7 TC[Scopus]:7 | Submit date:2018/10/30
Channel Loss  Cmos Equalizer  Continuous-time Linear Equalizer (Ctle)  Figure Of Merit (Fom)  Inductorless  Intersymbol Interference (Isi)  Low-frequency Equalization (Lfeq)  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
ELECTRONICS LETTERS, 2018,Volume: 54,Issue: 2
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite |  | TC[WOS]:3 TC[Scopus]:4 | Submit date:2018/10/30
Equalisers  Circuit Feedback  Analogue Circuits  Random Sequences  Binary Sequences  Cmos Analogue Integrated Circuits  Inductorless Analogue Equaliser  Low-frequency Equalisation Compensation  Lfeq  Low-frequency Channel Loss  Active Feedback Topology  Negative Capacitance Circuit  Data Jitter  Pseudorandom Binary Sequence  Cmos Technology  Loss 15 Db  Bit Rate 13 gBit  s  Size 65 Nm  Voltage 1  2 v  
A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS Journal article
Authors:  Chen, Yong;  Mak, Pui-In;  Boon, Chirn Chye;  Martins, Rui P.
Favorite |  | TC[WOS]:13 TC[Scopus]:9 | Submit date:2018/10/30
Cmos  Duobinary  Figure-of-merit (Fom)  Flip-flop (Ff)  Latch  Multiplexer (Mux)  Selector  Time-interleaved