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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xu, Dengke;  Wang, Guoxing;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/05/17
Adc  Background  Bandwidth  Calibration  Calibration.  Clocks  Finite Impulse Response Filters  Time-interleaved  Timing  Timing Mismatch  Tuning  Very Large Scale Integration  
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing Conference paper
Proceedings of the Custom Integrated Circuits Conference, Newport Beach, CA, USA, 24-27 April 2022
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Qi, Liang;  Xiao, Gangjun;  Martins, Rui P.
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Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs Conference paper
Proceedings - International SoC Design Conference 2021, ISOCC 2021, Jeju Island, Korea, Republic of, 06-09 October 2021
Authors:  Guo, Mingqiang;  Sin, Sai Weng;  Martins, Rui P.
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Adc  Background Calbration  Mismatch Calibration  Time-interleaved Converter  Timing Mismatch  
A 5 GS/s 29 mW Interleaved SAR ADC with 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications Journal article
IEEE Access, 2020,Volume: 8,Page: 138944-138954
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
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Analog-to-digital Converter (Adc)  Digital Background Calibration  Digital-mixing  Time-interleaved (Ti) Adc  Timing Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,Rui P.
Adobe PDF | Favorite |  | TC[WOS]:29 TC[Scopus]:30 | Submit date:2021/03/04
Analog-to-digital Converter (Adc)  Digital Background Calibration  Split Adc  Time-interleaved (Ti) Adc  Timing-skew Mismatch  
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration Journal article
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020,Volume: 55,Issue: 3,Page: 693-705
Authors:  Mingqiang Guo;  Jiaji Mao;  Sai-Weng Sin;  Hegong Wei;  Rui P. Martins
Favorite |  | TC[WOS]:29 TC[Scopus]:30 | Submit date:2022/08/20
Analog-to-Digital Converter (Adc), Digital Background CalibraTion, Split Adc, Time-interleaved (Ti) Adc, Timing-skew Mismatch  
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, JAPAN, JUN 09-14, 2019
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018,Volume: 65,Issue: 10,Page: 1380-1384
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Adobe PDF | Favorite |  | TC[WOS]:7 TC[Scopus]:7 | Submit date:2018/10/30
Analog-to-digital Conversion  Digital Background Calibration  Pipelined Adc  Split Adc  Opamp-sharing Technique  
Split-Based Time-interleaved ADC with Digital Background Timing-skew Calibration Conference paper
Giardini Naxos - Taormina, Italy, 12-15 June 2017
Authors:  Guo Mingqiang;  Sin Sai-Weng;  U Seng-Pan;  Rui P. Martins
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2022/08/20
Adc, Converters, Digital Background Calibration, Time-interleaving, split-Adc, Timing.