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A 108-nW 0.8-mm 2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 11,Page: 1-10
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/07/22
Approximate Computing  Convolutional Neural Network (Cnn)  Feature Extraction  Keyword Spotting (Kws)  Quantization  Reconfigurable  Sparsity  Switched-capacitor Circuits  Voice Activity Detection (Vad)  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Pui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/08
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022
Authors:  Lei Xuan;  Ka-Fai Un;  Chi-Seng Lam;  Rui P. Martins
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/06/14
Computational Cost , Convolutional Neural Network (Cnn) , Field-programmable Gate Array (Fpga) , Mobilenetv2 , Neural Network , Quantization  
A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS Conference paper
San Francisco, CA, 2022-02/20-26
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Pui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2022/07/26
Voice Activity Detection  Neural Networks  Feature Extraction  
A 108nW 0.8mm2Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, USA (Virtual), 20-28, Feb, 2022
Authors:  Chen, Feifei;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2022/05/17
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Foundations and Trends® in Integrated Circuits and Systems, 2021,Volume: 1,Issue: 2-3,Page: 72-216
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu;  Yan Lu;  Jun Yin;  Chi-Hang Chan;  Yong Chen;  Ka-Fai Un;  Mo Huang;  Minglei Zhang;  Yang Jiang;  Wei-Han Yu
Adobe PDF | Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3143-3147
Authors:  Li, Jixuan;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:6 TC[Scopus]:7 | Submit date:2021/09/20
Computation Efficiency  Convolutional Neural Network (Cnn)  Fpga  Object Recognition  Reconfigurability  
Learning across multi-stimulus enhances target recognition methods in SSVEP-based BCIs Journal article
Journal of Neural Engineering, 2020,Volume: 17,Issue: 1
Authors:  Wong,Chi Man;  Wan,Feng;  Wang,Boyu;  Wang,Ze;  Nan,Wenya;  Lao,Ka Fai;  Mak,Peng Un;  Vai,Mang I.;  Rosa,Agostinho
Favorite |  | TC[WOS]:39 TC[Scopus]:40 | Submit date:2021/03/11
Brain-computer Interface  Canonical Correlation Analysis  Learning Across Multi-stimulus  Steady-state Visual Evoked Potential  Task-related Component Analysis  
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 1,Page: 37-41
Authors:  Un,Ka Fai;  Zhang,Feifei;  Mak,Pui In;  Martins,Rui P.;  Zhu,Anding;  Staszewski,Robert Bogdan
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/03/09
Digital Baseband  Digital Transmitter (Dtx)  Linear Interpolation  Modulation  Noise Filtering  Out-of-band Noise  Quantization Noise  Replicas  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)