UM

Browse/Search Results:  1-10 of 133 Help

Selected(0)Clear Items/Page:    Sort:
Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate Conference paper
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Authors:  Xu, C.;  Zhang, J.;  Law, M. K.;  Jiang, Y.;  Zhao, X.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Resistance  Training  Solid modeling  Manufacturing processes  Linear feedback shift registers  Integrated circuit interconnections  Machine learning  
An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current Conference paper
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Authors:  Jiang, Y.;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Systematics  Switching frequency  DC-DC power converters  Switches  Topology  Steady-state  Solid state circuits  
A multi-path switched-capacitor-inductor hybrid DC-DC converter with reduced inductor loss and extended voltage conversion range Journal article
IEICE Electronics Express, 2021,Page: 1-6
Authors:  Ma, Q;  Zhang, X;  Jiang, Y.;  Hata, K;  Takamiya, M;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
DC-DC converter  DCR loss  hybrid topology  multi-path  switched-capacitor  voltage conversion range  
A 12V-to-1V switched-capacitor-assisted hybrid converter with dual-path charge conduction and zero-voltage switching Journal article
IEICE Electronics Express, 2021,Page: 1-6
Authors:  Zhang, X;  Ma, Q;  Jiang, Y.;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
hybrid buck converter  zero-voltage switching  high step-down  dual-path  DCR loss reduction  
Temperature tolerance electric cell-substrate impedance sensing (ECIS) for joint assessment of cell viability and vitality Journal article
ACS Sensors, 2021,Page: 1021-1021
Authors:  Yang, N.;  Hui, W.;  Dong, S.;  Zhang, X.;  Shao, L.;  Jia, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
cell viability  cell vitality  electric cell-substrate impedance sensing  ECIS  
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement Conference paper
IEEE Asian Solid State Circuit Conference
Authors:  Li, J.;  Chen, J.;  Un, K. F.;  Yu, W. H.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Computation efficiency  Convolutional neural network (CNN)  FPGA  object recognition  reconfigurability  
A High-Efficiency Dual-Antenna RF Energy Harvesting System using Full-Energy Extraction with Improved Input Power Response Journal article
IEEE Open Journal of Circuits and Systems, 2021,Page: 436-444
Authors:  Zhang, Z.;  Zhan, C.;  Law, M. K.;  Jiang, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Dual-antenna  full energy extraction  RF rectifier  RF energy harvesting  power combining  ultra-high frequency (UHF)  
A millimeter-wave CMOS VCO featuring a mode-ambiguity-aware multi-resonant-RCLM tank Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021,Page: 1-14
Authors:  Guo, H.;  Chen, Y.;  Yang, C.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
CMOS  VCO  
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021,Page: 1665-1669
Authors:  Wu, J.;  Leong, H. M.;  Jiang, Y.;  Law, M. K.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
CMOS  driver  fast transition  fully integrated  high-voltage (HV)  hybrid  pulse-frequency modulation (PFM)  switched-capacitor (SC)  voltage multiplier  
A sub-0.25pJ/bit 47.6- to-58.8Gb/s reference-less single-loop PAM-4 bang-bang CDR with a deliberately-current- mismatch frequency acquisition technique in 28nm CMOS Conference paper
Circuit Techniques for High-Speed Transceiver Front-Ends
Authors:  Zhao, X.;  Chen, Y.;  Mak, P. I.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
CDR  CMOS  Reference