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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
IEEE Journal of Solid-State Circuits, 2022,Volume: 57,Issue: 5,Page: 1480-1491
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:1 | Submit date:2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC Conference paper
Proceeding of 2021 Symposium on VLSI, N/A, 2021-06-15
Authors:  Wei, L.;  Zheng, Z.;  Markulic, N.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Kyoto, Japan, 13-19 June 2021
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui Paulo
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020,Volume: 67,Issue: 7,Page: 1174-1178
Authors:  Zhang, Jin;  Ren, Xiaoqian;  Liu, Shubin;  Chan, Chi Hang;  Zhu, Zhangming
Favorite |  | TC[WOS]:4 TC[Scopus]:7 | Submit date:2021/12/06
Analog-to-digital Converter (Adc)  Full Dynamic Adc  Pipelined Successive-approximation-register (Sar)  Pvt-stabilized Dynamic Amplification  Reused Comparator  
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020,Volume: 28,Issue: 4,Page: 1074-1078
Authors:  Sun, Jie;  Zhang, Minglei;  Qiu, Lei;  Wu, Jianhui;  Liu, Weiqiang
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date:2021/10/28
Background Calibration  Bit Weight  Dither Injection  Pipelined Sar Adc  Residue Increment  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
2020 IEEE International Solid- State Circuits Conference - (ISSCC), N/A, 2020-02-16
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.;  Chan, C. H.;  Craninckx, J.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 322-332
Authors:  Jiang,Wenning;  Zhu,Yan;  Zhang,Minglei;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite |  | TC[WOS]:19 TC[Scopus]:20 | Submit date:2021/03/09
Analog-to-digital Converter (Adc)  Gm-r Amplifier  Pipelined-successive Approximation Register (Sar) Adc  Residue Amplifier (Ra)  Sar  Sar-assisted Pipelined Adc  Temperature Compensation  
A 0.19 mm(2) 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS Conference paper
Taormina, ITALY, 1st International Symposium on Integrated Circuits and Systems (ISICAS)
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Zheng, Zi-Hao;  Li, Cheng;  Zhong, Jian-Yu;  Martins, Rui P.
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2018/10/30
Time-interleaved Adc  Sampling Front-end Design  Passive Sharing  Pipelined-sar Adc  Switch Bootstrap Technique  
A 0.19 mm2 10 b 2.3 GS/s 12-Way time-interleaved pipelined-sar ADC in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 11,Page: 3606-3616
Authors:  Zhu Y.;  Chan C.-H.;  Zheng Z.-H.;  Li C.;  Zhong J.-Y.;  Martins R.P.
Favorite |  | TC[WOS]:9 TC[Scopus]:9 | Submit date:2019/02/11
Passive Sharing  Pipelined-sar Adc  Sampling Front-end Design  Switch Bootstrap Technique  Time-interleaved Adc  
A 0.19mm2 10b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65nm CMOS Journal article
IEEE Transactions on Circuits and Systems I, 2018,Page: 3606-3616
Authors:  Zhu, Y.;  Chan, C. H.;  Zheng, Z. H.;  Li, C.;  Zhong, J. Y.;  Martins, R. P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2022/01/25
Time-interleaved Adc  Sampling Frontend Design  Passive Sharing  Pipelined-sar Adc  Switch Bootstrap Technique