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| A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors: Liang，Junhao; Sin，Sai Weng; Seng-Pan，U.; Maloberti，Franco; Martins，R. P.; Jiang，Hanjun
  Favorite | | TC[WOS]:0 TC[Scopus]:1 | Submit date：2021/03/09
CT sigma delta AD converter ECG high impedance non-invertering integrator Programmable integrator |
| A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors: Wang，Biao; Sin，Sai Weng; Seng-Pan，U.; Maloberti，Franco; Martins，R. P.
Favorite | | TC[WOS]:0 TC[Scopus]:0 | Submit date：2021/03/09
Data Weighted Averaging Linear-exponential Multi-Bit Incremental ADC Positive Feedback |
| A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 4,Page: 1161-1172
Authors: Wang，Biao; Sin，Sai Weng; Seng-Pan，S. P.U.; Maloberti，Franco; Martins，Rui P.
Favorite | | TC[WOS]:18 TC[Scopus]:19 | Submit date：2021/03/09
Analog-to-digital converter (ADC) data weighting average dynamic element matching (DEM) high linearity incremental ADC (IADC) linear-exponential accumulation mismatch error multi-bit notch sigma delta two phase |
| A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Honolulu, HI, JUN 18-22, 2018
Authors: Wang B.; Sin S.-W.; Seng-Pan U.; Malobertr F.; Martins R.P.
Favorite | | TC[WOS]:18 TC[Scopus]:7 | Submit date：2019/02/11 |
| Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC with Optimal Code Transfer Technique Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 2,Page: 489-501
Authors: Xing D.; Zhu Y.; Chan C.-H.; Maloberti F.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/11
Reference Interference Sar Adc Time-interleaved Scheme Two-step Sar Conversion |
| Accuracy-enhanced variance-based time-skew calibration using SAR as window detector Journal article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019,Volume: 27,Issue: 2,Page: 481-485
Authors: Liu J.; Chan C.-H.; Sin S.-W.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/02/13
Bandwidth Mismatches Split-digital To Analog Converter (Dac) Successive-approximation-register (Sar) Analog-to-digital Converter (Adc) Time-interleaved (Ti) Variance Based Window Detector (Wd) |
| A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Conference paper
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Authors: Jiang W.; Zhu Y.; Chan C.-H.; Murmann B.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:0 TC[Scopus]:4 | Submit date：2019/02/11
background calibration current integrating sampler Time-interleaved ADC timing skew |
| Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area Journal article
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018,Volume: 26,Issue: 11,Page: 2279-2289
Authors: Wang, Guan Cheng; Zhu, Yan; Chan, Chi-Hang; Seng-Pan, U.; Martins, Rui P.
Favorite | | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/01/17
Bridge digital-to-analog converter (DAC) gain error calibration successive approximation register (SAR) analog-to-digital converters (ADCs) testing signal generation (TSG) |
| A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems Conference paper
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Authors: Mao F.; Lu Y.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:0 TC[Scopus]:3 | Submit date：2019/02/11
delay compensation feedback loop implantable medical devices real time voltage doubler wireless power transfer |
| Analysis of common-mode interference and jitter of clock receiver circuits with improved topology Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018,Volume: 65,Issue: 6,Page: 1819-1829
Authors: Yang X.; Zhu Y.; Chan C.-H.; Seng-Pan U.; Martins R.P.
Favorite | | TC[WOS]:6 TC[Scopus]:7 | Submit date：2019/02/11
Isf Low Clock Jitter Circuit Self-bias |
