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Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022,Volume: 69,Issue: 2,Page: 495-505
Authors:  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Liu, Yueduo;  Bao, Rongxin;  Zhu, Zihao;  Yang, Shiheng;  Zhou, Xiong;  Li, Qiang;  Yin, Jun;  Mak, Pui In
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2022/03/04
Clocks  Delays  Jitter  Performance Evaluation  Phase Noise  Topology  Voltage-controlled Oscillators  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021,Volume: 68,Issue: 9,Page: 3108-3112
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In;  Li, Qiang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
Multiplying DLLs Book chapter
出自: Phase-Locked Frequency Generation and Clocking:Institution of Engineering and Technology, 2020, 页码: 645-664
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/12/03
Clocks  Delay Lock Loops  Jitter  Low-power Electronics  Multiplying Circuits  System-on-chip  Voltage-controlled Oscillators  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2019,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:11 TC[Scopus]:10 | Submit date:2021/03/09
Cmos  Divider-by-4  Dual Loop  Dynamic Latch  Figure-of-merit (Fom)  Frequency Detector (Fd)  Millimeter (Mm)-wave  Phase Detector (Pd)  Phase-locked Loop (Pll)  Voltage-controlled Oscillator (Vco)  Voltage-to-current Converter (Vic)  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:4 TC[Scopus]:4 | Submit date:2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 5,Page: 1351-1362
Authors:  Yang, Shiheng;  Yin, Jun;  Yi, Haidong;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite |  | TC[WOS]:25 TC[Scopus]:26 | Submit date:2021/10/28
Bluetooth Low Energy (Ble)  Cmos  Energy Harvesting  Master-slave Sampling Filter (Mssf)  Micropower Manager (Μpm)  Phase-locked Loop (Pll)  Power Amplifier (Pa)  Power Gating  Transmitter (Tx)  Ultralow-voltage (Ulv)  Voltage-controlled Oscillator (Vco)  
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and -249dB FOM Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, San Francisco, CA, United states, 2 11, 2018 - 2 15, 2018
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:17 | Submit date:2018/11/06
A 0.0056mm(2) All-Digital MDLL Using Edge Re-Extraction, Dual-Ring VCOs and a 0.3mW Block-Sharing Frequency Tracking Loop Achieving 292fs(rms) Jitter and-249dB FOM Conference paper
Authors:  Yang, Shiheng;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.;  IEEE
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2018/10/30