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A 4-μm diameter SPAD using less-doped N-Well guard ring in baseline 65-nm CMOS Journal article
IEEE Transactions on Electron Devices, 2020,Volume: 67,Issue: 5,Page: 2223-2225
Authors:  Lu,Xin;  Law,Man Kay;  Jiang,Yang;  Zhao,Xiaojin;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/04
Baseline CMOS  premature lateral breakdown  single-photon avalanche diode (SPAD)  small pitch  
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector Journal article
IEEE Access, 2020,Volume: 8,Page: 2222-2232
Authors:  Yang,Zunsong;  Chen,Yong;  Yang,Shiheng;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/03/09
CMOS  divider-by-4  dual loop  dynamic latch  figure-of-merit (FoM)  frequency detector (FD)  millimeter (mm)-wave  phase detector (PD)  phase-locked loop (PLL)  voltage-controlled oscillator (VCO)  voltage-to-current converter (VIC)  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
IEEE Solid-State Circuits Letters, 2020,Volume: 3,Page: 494-497
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/03/09
CMOS  in-band phase noise (PN)  narrow-pulse-sampling (NPS)  phase-locked loop (PLL)  reference (REF) spur  T-shape switch  type-I  voltage-controlled oscillator (VCO)  
Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 11,Page: 3118-3134
Authors:  Jiang,Yang;  Law,Man Kay;  Chen,Zhiyuan;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:7 TC[Scopus]:8 | Submit date:2021/03/09
Algebraic  boost converter  charge sharing loss  DC-DC  parasitic loss  power density  rational  series-parallel (SP)  switched-capacitor (SC)  voltage conversion ratio (VCR)  
A 0.003-mm2 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS Conference paper
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:4 | Submit date:2021/03/09
phase detector  phase locked loop (PLL)  reference spur  Ring voltage-controlled oscillator (VCO)  RMS jitter  
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 10,Page: 3991-4004
Authors:  Chen,Yong;  Mak,Pui In;  Yang,Zunsong;  Boon,Chirn Chye;  Martins,Rui P.
Favorite |  | TC[WOS]:5 TC[Scopus]:5 | Submit date:2021/03/09
active inductor (AI)  bandwidth (BW) extension  CMOS  current reuse  current-mode logic (CML)  current-mode transmitter  data-dependent jitter (DDJ)  figure-of-merit (FOM)  flip-flop (FF)  Fractional de-emphasis (DE)  hybrid delay line  latch  pulse-width-modulated (PWM)  unit interval (UI)  
Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS Journal article
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019,Volume: 66,Issue: 10,Page: 1768-1772
Authors:  Wu,Jiangchao;  Lei,Ka Chon;  Leong,Hou Man;  Jiang,Yang;  Law,Man Kay;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:2 | Submit date:2021/03/09
Charge compensation  driver  fully integrated  high-voltage  square wave  switched-capacitor  voltage multiplier  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019,Volume: 66,Issue: 9,Page: 3307-3316
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng;  Ieong,Chio In;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:2 TC[Scopus]:3 | Submit date:2021/03/09
bang-bang  Digital phase-locked loop (DPLL)  digital-to-time converter (DTC)  gain calibration  ring VCO  ultra-fast settling  ultra-low-power (ULP)  voltage-controlled oscillator (VCO)  
Multi-level Downsampling of Graph Signals via Improved Maximum Spanning Trees Journal article
INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE, 2019,Volume: 33,Issue: 3,Page: 1958005
Authors:  Zheng, Xianwei;  Tang, Yuan Yan;  Zhou, Jiantao;  Pan, Jianjia;  Yang, Shouzhi;  Li, Youfa;  Wang, Patrick S. P.
Favorite |  | TC[WOS]:1 TC[Scopus]:1 | Submit date:2019/04/16
Graph Signals  Maximum Spanning Tree  Graph Density  Unbalance Possibility  Imbalance Reduction  
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS Journal article
IEEE Journal of Solid-State Circuits, 2019,Volume: 54,Issue: 5,Page: 1351-1362
Authors:  Yang,Shiheng;  Yin,Jun;  Yi,Haidong;  Yu,Wei Han;  Mak,Pui In;  Martins,Rui P.
Favorite |  | TC[WOS]:8 TC[Scopus]:10 | Submit date:2021/03/09
Bluetooth low energy (BLE)  CMOS  energy harvesting  master-slave sampling filter (MSSF)  micropower manager (μPM)  phase-locked loop (PLL)  power amplifier (PA)  power gating  transmitter (TX)  ultralow-voltage (ULV)  voltage-controlled oscillator (VCO)