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A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Authors:  Zhang, Minglei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
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Background  input independent  time domain ADC  time-interleaved ADC  timing skew calibration  
A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture Conference paper
Proceedings of the Custom Integrated Circuits Conference
Authors:  Zhang, Yanbo;  Zhang, Jin;  Liu, Shubin;  Zhu, Zhangming;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
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27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, R. P.
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Bird's-eye view of analog and mixed-signal chips for the 21st century Journal article
International Journal of Circuit Theory and Applications, 2021
Authors:  Martins,Rui P.;  Mak,Pui In;  Chan,Chi Hang;  Yin,Jun;  Zhu,Yan;  Chen,Yong;  Lu,Yan;  Law,Man Kay;  Sin,Sai Weng
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analog and mixed-signal chips  analog digital interface  data converters  energy harvesting  integrated power converters  Internet of Everything  millimeter-wave frequency generators  wireless cellular transceivers  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:0 | Submit date:2021/09/20
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CTDSM)  Gain  high-speed noise-shaping SAR (NS-SAR).  Loading  Low-frequency noise  Modulation  preliminary sampling and quantization (PSQ) technique  Quantization (signal)  SAB-ELD-merged integrator  three-stage Opamp  Topology  Wideband  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
IEEE Journal of Solid-State Circuits, 2021
Authors:  Zheng, Zihao;  Wei, Lai;  Lagos, Jorge;  Martens, Ewout;  Zhu, Yan;  Chan, Chi Hang;  Craninckx, Jan;  Martins, Rui P.
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Analog-to-digital conversion  calibration  Calibration  dynamic amplifier (DA)  Hardware  Linearity  linearization technique  Pipeline processing  pipelined analog-to-digital converter (ADC).  Quantization (signal)  Signal resolution  System-on-chip  
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC with <1.5-ps Uncalibrated Quantization Steps Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 12,Page: 3225-3235
Authors:  Zhang,Minglei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:3 | Submit date:2021/03/04
Analog-to-digital converter (ADC)  and temperature (PVT) robustness  high-speed ADC  metastability  process  supply voltage  time interpolation  time residue  time-domain ADC  time-to-digital converter (TDC)  
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 6,Page: 1588-1598
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite |  | TC[WOS]:1 TC[Scopus]:2 | Submit date:2020/12/04
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CT-DSM)  preliminary sampling and quantization (PSQ) technique  single amplifier biquad (SAB)  successiveapproximation-register (SAR) architecture-based quantizer (QTZ)  
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC Journal article
IEEE Journal of Solid-State Circuits, 2020,Volume: 55,Issue: 2,Page: 312-321
Authors:  Song,Yan;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
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Alternative loading capacitor (ALC)  analog-to-digital converter (ADC)  multiplying digital-to-analog converter (MDAC) reusing  noise shaping (NS)  successive approximation register (SAR)-assisted pipeline  
A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Authors:  Zheng,Zihao;  Wei,Lai;  Lagos,Jorge;  Martens,Ewout;  Zhu,Yan;  Chan,Chi Hang;  Craninckx,Jan;  Martins,Rui P.
Favorite |  | TC[WOS]:0 TC[Scopus]:5 | Submit date:2021/03/04