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CENTRE FOR ENGINEERING RESEARCH AND TESTING
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A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur
Journal article
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023,Volume: 70,Issue: 4,Page: 1463-1475
Authors:
Huang, Yunbo
;
Chen, Yong
;
Zhao, Bo
;
Mak, Pui In
;
Martins, Rui P.
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TC[WOS]:
4
TC[Scopus]:
6
IF:
5.2
/
4.5
|
Submit date：2023/05/02
Cmos
Type-i Sampling Phase-locked Loop (S-pll)
Voltage-controlled Oscillator (Vco)
Reference (Ref) Feedthrough Suppression
Figure-of-merit (Fom)
Phase-detection Gain (Kpd)
Sampling Phase Detector (S-pd)
